366 lines
13 KiB
Systemverilog
366 lines
13 KiB
Systemverilog
`timescale 1ns / 1ps
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`include "interfaces.svh"
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module reflectometer_tb;
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//------------------------------------------------------------
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// Параметры
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//------------------------------------------------------------
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localparam int unsigned DAC_DATA_WIDTH = 14;
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localparam int unsigned ADC_DATA_WIDTH = 12;
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localparam LOGIC_ZERO_LEVEL = 0; // DAC -5V for logic zero
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localparam VOLTAGE_ZERO_LEVEL = 2**(DAC_DATA_WIDTH-1); // DAC 0V for logic zero
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localparam PACK_FACTOR = 1; // not used in TB
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localparam PROCESS_MODE = 1; // 0 - uint, 1 - int
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localparam ACCUM_WIDTH = 32; // accumulator number bit witdth
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localparam N_MAX = 4096; // max value of windows to average by experiments
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localparam PACKET_SIZE = 1024; // bytes per UDP packet
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localparam int REQUEST_TIMEOUT = 3 * PACKET_SIZE; // timeout for packet receiving from accumulator
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localparam ZERO_LEVEL = LOGIC_ZERO_LEVEL; // "logic" VS "voltage"
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localparam CLK_ETH_PHY_PERIOD = 8.000; // 125 MHz
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localparam CLK_REF_PERIOD = 5.000; // 200 MHz
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//------------------------------------------------------------
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// Глобальные перменные
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//------------------------------------------------------------
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int unsigned WINDOW_SIZE = 65; // fixed subwindow size to average by time
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//------------------------------------------------------------
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// Тактовые сигналы и сброс
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//------------------------------------------------------------
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logic clk_ref = 1'b0; // 200 MHz
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logic clk_eth_phy = 1'b0; // common for RX & TX
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logic rst_n = 1'b0;
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//------------------------------------------------------------
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// Управление и конфиг DUT
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//------------------------------------------------------------
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logic [31:0] window_size;
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// AXI-S интерфейс для управления
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axis_if axis_control_if (
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.clk(clk_eth_phy),
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.rst_n(rst_n)
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);
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//------------------------------------------------------------
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// Входы DUT
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//------------------------------------------------------------
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// ADC интерфейс
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wire clk_adc;
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wire adc_otr;
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wire [ADC_DATA_WIDTH-1:0] adc_data;
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//------------------------------------------------------------
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// Выходы
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//------------------------------------------------------------
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// Статусы
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wire mmcm_locked;
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wire workflow_done;
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wire processing_done;
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// DAC интерфейс
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wire clk_dac;
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wire dac_wrt;
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wire [DAC_DATA_WIDTH-1:0] dac_data;
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// AXI-S интерфейс для данных
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axis_if axis_accumulator_if (
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.clk(clk_eth_phy),
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.rst_n(rst_n)
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);
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//------------------------------------------------------------
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// Внутренние сигналы тестбенча
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//------------------------------------------------------------
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// Интерфейс хендшейка с MAC-PHY
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wire send_request;
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logic request_ready;
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// Сигнал между ЦАП и АЦП
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real signal_voltage;
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//------------------------------------------------------------
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// Virtual DAC
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//------------------------------------------------------------
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virtual_dac_model #( // default voltage range is +/- 5V
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.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
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// ,.VOLTAGE_GAIN(2)
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) virtual_dac (
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.clk_i(clk_dac),
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.wrt_i(dac_wrt),
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.data_i(dac_data),
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.voltage_o(signal_voltage)
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);
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//------------------------------------------------------------
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// Virtual ADC
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//------------------------------------------------------------
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virtual_adc_model #( // default voltage range is +/- 5V
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.ADC_DATA_WIDTH(ADC_DATA_WIDTH)
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) virtual_adc (
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.clk_i(clk_adc),
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.voltage_i(signal_voltage),
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.otr_o(adc_otr),
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.data_o(adc_data)
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);
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//------------------------------------------------------------
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// Statistics processing
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//------------------------------------------------------------
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//------------------------------------------------------------
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// Config handler
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//------------------------------------------------------------
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//------------------------------------------------------------
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// DUT
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//------------------------------------------------------------
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reflectometer_top #(
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.DAC_DATA_WIDTH(DAC_DATA_WIDTH),
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.ADC_DATA_WIDTH(ADC_DATA_WIDTH),
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.PACK_FACTOR(PACK_FACTOR),
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.PROCESS_MODE(PROCESS_MODE),
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.ZERO_LEVEL(ZERO_LEVEL),
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.ACCUM_WIDTH(ACCUM_WIDTH),
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.N_MAX(N_MAX),
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.PACKET_SIZE(PACKET_SIZE)
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) DUT (
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.clk_in(clk_ref),
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.rst_n(rst_n),
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// Status
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.locked(mmcm_locked),
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.workflow_done(workflow_done),
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.processing_done(processing_done),
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// Accumulator AXI-S bus
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.clk_axis_accumulator(clk_eth_phy), // GMII PHY RX clock
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.axis_accumulator(axis_accumulator_if.master),
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// Control AXI-S bus
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.clk_axis_control(clk_eth_phy), // GMII PHY TX clock
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.axis_control(axis_control_if.slave),
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.window_size(window_size), // direct signal crutch (old controller)
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// RTL-MAC handshake
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.request_ready(request_ready),
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.send_request(send_request),
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// DAC
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.dac_clk_o(clk_dac),
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.dac_data(dac_data),
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.dac_wrt(dac_wrt),
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// ADC
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.adc_clk_o(clk_adc),
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.adc_data(adc_data),
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.adc_otr(adc_otr)
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);
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assign window_size = WINDOW_SIZE;
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//------------------------------------------------------------
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// Тактовые сигналы
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//------------------------------------------------------------
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initial begin
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forever #(CLK_REF_PERIOD/2) clk_ref = ~clk_ref;
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end
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initial begin
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forever #(CLK_ETH_PHY_PERIOD/2) clk_eth_phy = ~clk_eth_phy;
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end
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//------------------------------------------------------------
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// Таски для тестирования
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//------------------------------------------------------------
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// Таски работы с AXI-Stream
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task automatic dut_soft_reset(virtual axis_if#(8).tb vif);
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logic [7:0] tx_packet[];
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tx_packet = '{8'h0f};
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vif.master_send(tx_packet);
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endtask
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task automatic dut_start(virtual axis_if#(8).tb vif);
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logic [7:0] tx_packet[];
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tx_packet = '{8'hf0};
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vif.master_send(tx_packet);
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endtask
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task automatic dut_send_system_config(
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virtual axis_if#(8).tb vif,
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input logic [31:0] pulse_width,
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input logic [31:0] pulse_period,
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input logic [15:0] pulse_num,
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input logic [13:0] pulse_height, // achtung! p_height strictly must have 14 bits of width
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input logic [31:0] pulse_period_adc
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);
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// Создаем временный фиксированный массив и упаковываем всё одной строкой
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logic [7:0] tx_packet[];
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// Ахтунг, 14-битный ЦАП захардкожен
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if (DAC_DATA_WIDTH != 14)
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$display("[WARNING] -dut_send_system_config- Default pulse height (DAC bitwidth) is equal to 14. Be aware, controller packet structure is coded for 14 bits");
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tx_packet = '{
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8'h88, // Команда
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pulse_width[7:0], pulse_width[15:8], pulse_width[23:16], pulse_width[31:24],
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pulse_period[7:0], pulse_period[15:8], pulse_period[23:16], pulse_period[31:24],
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pulse_num[7:0], pulse_num[15:8], pulse_height[7:0], 8'({2'b00, pulse_height[13:8]}),
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pulse_period_adc[7:0], pulse_period_adc[15:8], pulse_period_adc[23:16], pulse_period_adc[31:24]
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};
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vif.master_send(tx_packet);
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endtask
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// Таски сбора статистики
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task automatic dut_read_output(
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virtual axis_if#(8).tb vif,
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input int sample_num,
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input bit randomize_recv_delays,
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output int output_data[]
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);
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logic [7:0] rx_packet[];
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logic [ACCUM_WIDTH-1:0] data_packet[];
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int packet_num = $ceil(real'(sample_num / WINDOW_SIZE) / real'(PACKET_SIZE));
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int numbers_per_packet = PACKET_SIZE/(ACCUM_WIDTH/8);
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int idx = 0, timeout_flag = 0;
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int packet_counter = 0;
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if (sample_num % WINDOW_SIZE) begin
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$display("[TB] -dut_read_output- Error, sample_num must be multiple of WINDOW_SIZE: %0d %% %0d = %0d", sample_num, WINDOW_SIZE, sample_num % WINDOW_SIZE);
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$finish;
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end
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data_packet = new[numbers_per_packet];
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output_data = new[numbers_per_packet * packet_num];
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// count send_request pulses (equal to number of packets)
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fork
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begin : packet_counter_proc
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forever begin
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@(posedge clk_eth_phy);
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if(send_request === 1)
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packet_counter++;
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end
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end
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join_none
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// Wait until reflectometer done sampling and averaging
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wait(processing_done == 1);
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// recv loop
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for (int i = 0; i < packet_num; i++) begin
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if (randomize_recv_delays)
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repeat($urandom_range(0, 500)) @(posedge clk_eth_phy);
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timeout_flag = 0;
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fork
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begin : receive_packet_proc
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request_ready = 1;
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vif.slave_recv(rx_packet);
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request_ready = 0;
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end
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begin : timeout_proc
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repeat(REQUEST_TIMEOUT) @(posedge clk_eth_phy);
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timeout_flag = 1;
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end
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join_any
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disable receive_packet_proc;
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disable timeout_proc;
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if (timeout_flag) begin
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$display("[ERROR] -dut_read_output- Timeout detected when receiving packet");
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$finish;
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end
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if (rx_packet.size() != PACKET_SIZE) begin
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$display("[ERROR] -dut_read_output- Wrong packet size received: %0d bytes received, %0d bytes expected", rx_packet.size(), PACKET_SIZE);
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end
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// unpack values
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data_packet = {<< byte {rx_packet}};
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data_packet = {<< ACCUM_WIDTH {data_packet}};
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// copy and convert values
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for (int j = 0; j < data_packet.size(); j++) begin
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output_data[i * data_packet.size() + j] = int'(data_packet[j]);
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end
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end
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disable packet_counter_proc;
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if (packet_counter != packet_num) begin
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$display("[ERROR] -dut_read_output- Wrong number of packets received: %0d received, %0d expected", packet_counter, packet_num);
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$finish;
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end
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// Wait until full transaction of data is complete
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timeout_flag = 0;
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fork
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wait(workflow_done == 1);
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begin : timeout_proc
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repeat(10) @(negedge clk_adc); // sampler clock
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timeout_flag = 1;
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end
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join_any
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disable timeout_proc;
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if (timeout_flag) begin
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$display("[ERROR] -dut_read_output- Timeout detected when awaiting for finish pulse");
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$finish;
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end
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endtask
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// Основная таска типового теста
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// todo
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//------------------------------------------------------------
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// ОСНОВНОЙ ПРОЦЕСС ТЕСТИРОВАНИЯ
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//------------------------------------------------------------
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initial begin
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int output_data[];
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automatic virtual axis_if.tb control_vif = axis_control_if.tb;
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automatic virtual axis_if.tb accumulator_vif = axis_accumulator_if.tb;
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$display("[TB] DUT initializaton");
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// Инициализация
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request_ready = 0;
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rst_n = 0;
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#100;
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rst_n = 1;
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wait(mmcm_locked === 1'b1);
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#150;
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$display("[TB] MMCM locked");
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dut_soft_reset(control_vif);
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#100;
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// Тесты
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$display("[TB] Tests start");
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dut_send_system_config(
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.vif(control_vif),
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.pulse_width(32'd123),
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.pulse_period(32'd5000),
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.pulse_num(16'd1),
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.pulse_height(14'd15000), // 0V
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.pulse_period_adc(32'd2600)
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);
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#100;
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dut_start(control_vif);
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dut_read_output(
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.vif(accumulator_vif),
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.sample_num(2600),
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.randomize_recv_delays(0),
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.output_data(output_data)
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);
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$display("Received %0d numbers", output_data.size());
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for (int i = 0; i < output_data.size(); i++) begin
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$write("%0d ", output_data[i]);
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end
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$display("");
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$display("[TB] ALL PASSED");
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$finish;
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end
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endmodule
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