dev/design #8
@ -1,3 +1,10 @@
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||||
# reflectometer_fpga_project
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Проект по разработке аппаратной вычислительной части для отпического рефлектометра для обнаружения утечек.
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Проект по разработке аппаратной вычислительной части для оптического рефлектометра для обнаружения утечек.
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## Структура
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- constaints: констрейны под ПЛИСы
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- designs: разные сборные дизайны, включая полный проект
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- rtl: код блоков, в каждой папке есть src и tests
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- scripts: скрипты для сборки
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- software: программные скрипты
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172
constraints/ax7102.xdc
Normal file
172
constraints/ax7102.xdc
Normal file
@ -0,0 +1,172 @@
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# === iostandard ===
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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# === SPI flash config ===
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
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set_property CONFIG_MODE SPIx4 [current_design]
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set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
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# === clock config ===
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create_clock -period 5.000 [get_ports sys_clk_p]
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set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_p]
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set_property PACKAGE_PIN R4 [get_ports sys_clk_p]
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set_property PACKAGE_PIN T4 [get_ports sys_clk_n]
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set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n]
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# === reset button ===
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set_property IOSTANDARD LVCMOS15 [get_ports rst_n]
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set_property PACKAGE_PIN T6 [get_ports rst_n]
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# === leds ===
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set_property IOSTANDARD LVCMOS33 [get_ports {led[*]}]
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set_property PACKAGE_PIN C17 [get_ports {led[0]}]
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set_property PACKAGE_PIN D17 [get_ports {led[1]}]
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set_property PACKAGE_PIN V20 [get_ports {led[2]}]
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set_property PACKAGE_PIN U20 [get_ports {led[3]}]
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# === 1Gb ethernet PHY ===
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set_property PACKAGE_PIN V10 [get_ports e_mdio]
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set_property IOSTANDARD LVCMOS33 [get_ports e_mdio]
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set_property PACKAGE_PIN W10 [get_ports e_mdc]
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set_property IOSTANDARD LVCMOS33 [get_ports e_mdc]
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set_property PULLTYPE PULLUP [get_ports e_mdc]
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set_property SLEW SLOW [get_ports e_mdio]
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set_property PULLTYPE PULLUP [get_ports e_mdio]
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# eth rx
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create_clock -period 8.000 -name rx_clk [get_ports e_rxc]
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set_property IOSTANDARD LVCMOS33 [get_ports e_rxc]
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set_property PACKAGE_PIN K18 [get_ports e_rxc]
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set_property IOSTANDARD LVCMOS33 [get_ports e_rxdv]
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set_property PACKAGE_PIN M22 [get_ports e_rxdv]
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set_property IOSTANDARD LVCMOS33 [get_ports e_rxer]
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set_property PACKAGE_PIN N19 [get_ports e_rxer]
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set_property IOSTANDARD LVCMOS33 [get_ports {e_rxd[*]}]
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set_property PACKAGE_PIN N22 [get_ports {e_rxd[0]}]
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set_property PACKAGE_PIN H18 [get_ports {e_rxd[1]}]
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set_property PACKAGE_PIN H17 [get_ports {e_rxd[2]}]
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set_property PACKAGE_PIN K19 [get_ports {e_rxd[3]}]
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set_property PACKAGE_PIN M21 [get_ports {e_rxd[4]}]
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set_property PACKAGE_PIN L21 [get_ports {e_rxd[5]}]
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set_property PACKAGE_PIN N20 [get_ports {e_rxd[6]}]
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set_property PACKAGE_PIN M20 [get_ports {e_rxd[7]}]
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# eth tx
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set_property IOSTANDARD LVCMOS33 [get_ports e_txc]
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set_property PACKAGE_PIN J17 [get_ports e_txc]
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set_property IOSTANDARD LVCMOS33 [get_ports e_gtxc]
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set_property PACKAGE_PIN L18 [get_ports e_gtxc]
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set_property IOSTANDARD LVCMOS33 [get_ports e_txen]
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set_property PACKAGE_PIN M16 [get_ports e_txen]
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set_property IOSTANDARD LVCMOS33 [get_ports e_txer]
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set_property PACKAGE_PIN M13 [get_ports e_txer]
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set_property IOSTANDARD LVCMOS33 [get_ports {e_txd[*]}]
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set_property PACKAGE_PIN M15 [get_ports {e_txd[0]}]
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set_property PACKAGE_PIN L14 [get_ports {e_txd[1]}]
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set_property PACKAGE_PIN K16 [get_ports {e_txd[2]}]
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set_property PACKAGE_PIN L16 [get_ports {e_txd[3]}]
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set_property PACKAGE_PIN K17 [get_ports {e_txd[4]}]
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set_property PACKAGE_PIN L20 [get_ports {e_txd[5]}]
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set_property PACKAGE_PIN L19 [get_ports {e_txd[6]}]
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set_property PACKAGE_PIN L13 [get_ports {e_txd[7]}]
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set_property IOSTANDARD LVCMOS33 [get_ports e_reset]
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set_property PACKAGE_PIN L15 [get_ports e_reset]
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create_clock -period 8.000 -name tx_clk [get_ports e_gtxc]
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set_false_path -reset_path -from [get_clocks sys_clk_p] -to [get_clocks rx_clk]
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# === ADC an9238 (J4 header) ===
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set_property PACKAGE_PIN K14 [get_ports ch2_clk]
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set_property PACKAGE_PIN K13 [get_ports {ch2_data[0]}]
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set_property PACKAGE_PIN H14 [get_ports {ch2_data[1]}]
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set_property PACKAGE_PIN J14 [get_ports {ch2_data[2]}]
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set_property PACKAGE_PIN H15 [get_ports {ch2_data[3]}]
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set_property PACKAGE_PIN J15 [get_ports {ch2_data[4]}]
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set_property PACKAGE_PIN G13 [get_ports {ch2_data[5]}]
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set_property PACKAGE_PIN H13 [get_ports {ch2_data[6]}]
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set_property PACKAGE_PIN J21 [get_ports {ch2_data[7]}]
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set_property PACKAGE_PIN J20 [get_ports {ch2_data[8]}]
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set_property PACKAGE_PIN G16 [get_ports {ch2_data[9]}]
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set_property PACKAGE_PIN G15 [get_ports {ch2_data[10]}]
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set_property PACKAGE_PIN H19 [get_ports {ch2_data[11]}]
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set_property PACKAGE_PIN J19 [get_ports ch2_otr]
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set_property PACKAGE_PIN J16 [get_ports ch1_data[1]]
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set_property PACKAGE_PIN F15 [get_ports ch1_data[0]]
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set_property PACKAGE_PIN K22 [get_ports ch1_data[3]]
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set_property PACKAGE_PIN K21 [get_ports ch1_data[2]]
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set_property PACKAGE_PIN H22 [get_ports ch1_data[5]]
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set_property PACKAGE_PIN J22 [get_ports ch1_data[4]]
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set_property PACKAGE_PIN G20 [get_ports ch1_data[7]]
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set_property PACKAGE_PIN H20 [get_ports ch1_data[6]]
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set_property PACKAGE_PIN G22 [get_ports ch1_data[9]]
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set_property PACKAGE_PIN G21 [get_ports ch1_data[8]]
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set_property PACKAGE_PIN D22 [get_ports ch1_data[11]]
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set_property PACKAGE_PIN E22 [get_ports ch1_data[10]]
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set_property PACKAGE_PIN D21 [get_ports ch1_clk]
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set_property PACKAGE_PIN E21 [get_ports ch1_otr]
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set_property IOSTANDARD LVCMOS33 [get_ports ch2_clk]
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set_property IOSTANDARD LVCMOS33 [get_ports {ch2_data[*]}]
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set_property IOSTANDARD LVCMOS33 [get_ports ch2_otr]
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set_property IOSTANDARD LVCMOS33 [get_ports {ch1_data[*]}]
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set_property IOSTANDARD LVCMOS33 [get_ports ch1_clk]
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set_property IOSTANDARD LVCMOS33 [get_ports ch1_otr]
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set_property SLEW FAST [get_ports ch2_clk]
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# === DAC an9767(J5 header) ===
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set_property PACKAGE_PIN F13 [get_ports {da1_clk}]
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set_property PACKAGE_PIN F14 [get_ports {da1_wrt}]
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set_property PACKAGE_PIN AB15 [get_ports {da1_data[13]}]
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set_property PACKAGE_PIN AA15 [get_ports {da1_data[12]}]
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set_property PACKAGE_PIN AA14 [get_ports {da1_data[11]}]
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set_property PACKAGE_PIN Y13 [get_ports {da1_data[10]}]
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set_property PACKAGE_PIN AB17 [get_ports {da1_data[9]}]
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set_property PACKAGE_PIN AB16 [get_ports {da1_data[8]}]
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set_property PACKAGE_PIN AA16 [get_ports {da1_data[7]}]
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set_property PACKAGE_PIN Y16 [get_ports {da1_data[6]}]
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set_property PACKAGE_PIN AB12 [get_ports {da1_data[5]}]
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set_property PACKAGE_PIN AB11 [get_ports {da1_data[4]}]
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set_property PACKAGE_PIN Y14 [get_ports {da1_data[3]}]
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set_property PACKAGE_PIN W14 [get_ports {da1_data[2]}]
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set_property PACKAGE_PIN C19 [get_ports {da1_data[1]}]
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set_property PACKAGE_PIN C18 [get_ports {da1_data[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {da1_data[*]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {da1_wrt}]
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set_property IOSTANDARD LVCMOS33 [get_ports {da1_clk}]
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set_property PACKAGE_PIN E14 [get_ports da2_clk]
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set_property PACKAGE_PIN E13 [get_ports da2_wrt]
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set_property PACKAGE_PIN D15 [get_ports {da2_data[13]}]
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set_property PACKAGE_PIN D14 [get_ports {da2_data[12]}]
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set_property PACKAGE_PIN B13 [get_ports {da2_data[11]}]
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set_property PACKAGE_PIN C13 [get_ports {da2_data[10]}]
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set_property PACKAGE_PIN AB13 [get_ports {da2_data[9]}]
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set_property PACKAGE_PIN AA13 [get_ports {da2_data[8]}]
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set_property PACKAGE_PIN A19 [get_ports {da2_data[7]}]
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set_property PACKAGE_PIN A18 [get_ports {da2_data[6]}]
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set_property PACKAGE_PIN E18 [get_ports {da2_data[5]}]
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set_property PACKAGE_PIN F18 [get_ports {da2_data[4]}]
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set_property PACKAGE_PIN F20 [get_ports {da2_data[3]}]
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set_property PACKAGE_PIN F19 [get_ports {da2_data[2]}]
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set_property PACKAGE_PIN A20 [get_ports {da2_data[1]}]
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set_property PACKAGE_PIN B20 [get_ports {da2_data[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports da2_clk]
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set_property IOSTANDARD LVCMOS33 [get_ports da2_wrt]
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set_property IOSTANDARD LVCMOS33 [get_ports {da2_data[*]}]
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@ -59,39 +59,82 @@ set_property SLEW FAST [get_ports {rgmii_txd[*]}]
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create_clock -period 8.000 [get_ports rgmii_rxc]
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# === DAC (J11 header) ===
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set_property IOSTANDARD LVCMOS33 [get_ports p2_clk]
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set_property IOSTANDARD LVCMOS33 [get_ports p2_wrt]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[13]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[12]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[11]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[10]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[9]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[8]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[7]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[6]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[5]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[4]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[0]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports p2_clk]
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#set_property IOSTANDARD LVCMOS33 [get_ports p2_wrt]
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#set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[13]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[12]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[11]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[10]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[9]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[8]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[7]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[6]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[5]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[4]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[3]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[2]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[1]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {p2_data[0]}]
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#set_property SLEW FAST [get_ports p2_clk]
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#set_property PACKAGE_PIN C18 [get_ports p2_clk]
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#set_property PACKAGE_PIN C19 [get_ports p2_wrt]
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#set_property PACKAGE_PIN B17 [get_ports {p2_data[13]}]
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#set_property PACKAGE_PIN B18 [get_ports {p2_data[12]}]
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#set_property PACKAGE_PIN D17 [get_ports {p2_data[11]}]
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#set_property PACKAGE_PIN C17 [get_ports {p2_data[10]}]
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#set_property PACKAGE_PIN A15 [get_ports {p2_data[9]}]
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#set_property PACKAGE_PIN A16 [get_ports {p2_data[8]}]
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#set_property PACKAGE_PIN B15 [get_ports {p2_data[7]}]
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#set_property PACKAGE_PIN B16 [get_ports {p2_data[6]}]
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#set_property PACKAGE_PIN A13 [get_ports {p2_data[5]}]
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#set_property PACKAGE_PIN A14 [get_ports {p2_data[4]}]
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#set_property PACKAGE_PIN E16 [get_ports {p2_data[3]}]
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#set_property PACKAGE_PIN D16 [get_ports {p2_data[2]}]
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#set_property PACKAGE_PIN C14 [get_ports {p2_data[1]}]
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#set_property PACKAGE_PIN C15 [get_ports {p2_data[0]}]
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|
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# === ADC an9238 (J11 header) ===
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set_property PACKAGE_PIN G21 [get_ports ch2_clk]
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set_property PACKAGE_PIN G22 [get_ports {ch2_data[0]}]
|
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set_property PACKAGE_PIN C22 [get_ports {ch2_data[1]}]
|
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set_property PACKAGE_PIN B22 [get_ports {ch2_data[2]}]
|
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set_property PACKAGE_PIN F19 [get_ports {ch2_data[3]}]
|
||||
set_property PACKAGE_PIN F20 [get_ports {ch2_data[4]}]
|
||||
set_property PACKAGE_PIN D20 [get_ports {ch2_data[5]}]
|
||||
set_property PACKAGE_PIN C20 [get_ports {ch2_data[6]}]
|
||||
set_property PACKAGE_PIN A18 [get_ports {ch2_data[7]}]
|
||||
set_property PACKAGE_PIN A19 [get_ports {ch2_data[8]}]
|
||||
set_property PACKAGE_PIN B20 [get_ports {ch2_data[9]}]
|
||||
set_property PACKAGE_PIN A20 [get_ports {ch2_data[10]}]
|
||||
set_property PACKAGE_PIN F18 [get_ports {ch2_data[11]}]
|
||||
set_property PACKAGE_PIN E18 [get_ports ch2_otr]
|
||||
set_property PACKAGE_PIN C18 [get_ports ch1_data[1]]
|
||||
set_property PACKAGE_PIN C19 [get_ports ch1_data[0]]
|
||||
set_property PACKAGE_PIN B17 [get_ports ch1_data[3]]
|
||||
set_property PACKAGE_PIN B18 [get_ports ch1_data[2]]
|
||||
set_property PACKAGE_PIN D17 [get_ports ch1_data[5]]
|
||||
set_property PACKAGE_PIN C17 [get_ports ch1_data[4]]
|
||||
set_property PACKAGE_PIN A15 [get_ports ch1_data[7]]
|
||||
set_property PACKAGE_PIN A16 [get_ports ch1_data[6]]
|
||||
set_property PACKAGE_PIN B15 [get_ports ch1_data[9]]
|
||||
set_property PACKAGE_PIN B16 [get_ports ch1_data[8]]
|
||||
set_property PACKAGE_PIN A13 [get_ports ch1_data[11]]
|
||||
set_property PACKAGE_PIN A14 [get_ports ch1_data[10]]
|
||||
set_property PACKAGE_PIN E16 [get_ports ch1_clk]
|
||||
set_property PACKAGE_PIN D16 [get_ports ch1_otr]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports ch2_clk]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {ch2_data[*]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports ch2_otr]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {ch1_data[*]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports ch1_clk]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports ch1_otr]
|
||||
|
||||
# 1 bit DAC)))
|
||||
set_property PACKAGE_PIN E17 [get_ports debug_dac]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports debug_dac]
|
||||
|
||||
set_property SLEW FAST [get_ports p2_clk]
|
||||
|
||||
set_property PACKAGE_PIN C18 [get_ports p2_clk]
|
||||
set_property PACKAGE_PIN C19 [get_ports p2_wrt]
|
||||
set_property PACKAGE_PIN B17 [get_ports {p2_data[13]}]
|
||||
set_property PACKAGE_PIN B18 [get_ports {p2_data[12]}]
|
||||
set_property PACKAGE_PIN D17 [get_ports {p2_data[11]}]
|
||||
set_property PACKAGE_PIN C17 [get_ports {p2_data[10]}]
|
||||
set_property PACKAGE_PIN A15 [get_ports {p2_data[9]}]
|
||||
set_property PACKAGE_PIN A16 [get_ports {p2_data[8]}]
|
||||
set_property PACKAGE_PIN B15 [get_ports {p2_data[7]}]
|
||||
set_property PACKAGE_PIN B16 [get_ports {p2_data[6]}]
|
||||
set_property PACKAGE_PIN A13 [get_ports {p2_data[5]}]
|
||||
set_property PACKAGE_PIN A14 [get_ports {p2_data[4]}]
|
||||
set_property PACKAGE_PIN E16 [get_ports {p2_data[3]}]
|
||||
set_property PACKAGE_PIN D16 [get_ports {p2_data[2]}]
|
||||
set_property PACKAGE_PIN C14 [get_ports {p2_data[1]}]
|
||||
set_property PACKAGE_PIN C15 [get_ports {p2_data[0]}]
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
# Директория с тестовыми проектами под ПЛИСу
|
||||
|
||||
- eth_ctrl_debug: проект с ethernet и контроллером. Позволяет через ILA проверить, что пакет правильно принимается и что значения правильно выставляются.
|
||||
|
||||
- eth_generator: проект на базе eth_ctrl_debug, в который включен генератор импульсов. В паре с ЦАП можно через консольку по Ethernet запускать генерацию разных импульсов.
|
||||
- adc_dac_synchronizer: проект для тестирования и отладки связки сэмплер + контроллер + генератор, проверки синхронизации между импульсами.
|
||||
- reflectometer_base: базовый проект рефлектометра без внешних интерфейсов, только I/O через AXI Stream.
|
||||
- reflectometer_prototype: тестовый проект под AX7102 с управлением и отправкой данных по ethernet.
|
||||
56
designs/adc_dac_synchoronizer/Makefile
Normal file
56
designs/adc_dac_synchoronizer/Makefile
Normal file
@ -0,0 +1,56 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xc7a100tfgg484-2
|
||||
FPGA_TOP = sync_top
|
||||
FPGA_ARCH = artix7
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
|
||||
|
||||
include ../../scripts/vivado.mk
|
||||
|
||||
|
||||
SYN_FILES += $(sort $(shell find ../../rtl/sampler/src -type f -name '*.sv'))
|
||||
SYN_FILES += $(sort $(shell find ../../rtl/generator/src -type f -name '*.sv'))
|
||||
SYN_FILES += sync_top.sv
|
||||
|
||||
XCI_FILES += $(sort $(shell find ip/ -type f -name '*.xci'))
|
||||
|
||||
XDC_FILES += ../../constraints/ax7102.xdc
|
||||
XDC_FILES += debug.xdc
|
||||
|
||||
SYN_FILES += tb_sync_top.sv
|
||||
SIM_TOP = tb_top
|
||||
|
||||
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 16 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
10
designs/adc_dac_synchoronizer/debug.xdc
Normal file
10
designs/adc_dac_synchoronizer/debug.xdc
Normal file
@ -0,0 +1,10 @@
|
||||
# Primary clocks
|
||||
create_clock -name eth_clk -period 8.000 [get_ports dac_clk_in]
|
||||
create_clock -name acc_clk -period 15.385 [get_ports adc_clk_in]
|
||||
|
||||
|
||||
# Asynchronous clock groups
|
||||
|
||||
set_clock_groups -name ASYNC_ETH_ACC -asynchronous \
|
||||
-group [get_clocks eth_clk] \
|
||||
-group [get_clocks acc_clk]
|
||||
136
designs/adc_dac_synchoronizer/sync_top.sv
Normal file
136
designs/adc_dac_synchoronizer/sync_top.sv
Normal file
@ -0,0 +1,136 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module sync_top
|
||||
#(
|
||||
parameter int unsigned DAC_DATA_WIDTH = 14,
|
||||
parameter int unsigned ADC_DATA_WIDTH = 12,
|
||||
parameter int unsigned PACK_FACTOR = 1,
|
||||
parameter int unsigned PROCESS_MODE = 0
|
||||
)
|
||||
(
|
||||
input adc_clk_in,
|
||||
input adc_rst,
|
||||
|
||||
input dac_clk_in,
|
||||
input dac_rst,
|
||||
|
||||
input dac_start,
|
||||
|
||||
input [31:0] pulse_width,
|
||||
input [31:0] pulse_period,
|
||||
input [DAC_DATA_WIDTH-1:0] pulse_height,
|
||||
input [15:0] pulse_num,
|
||||
input [31:0] smp_num,
|
||||
|
||||
output logic [ADC_DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata,
|
||||
output logic m_axis_tvalid
|
||||
);
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Internal signals
|
||||
//------------------------------------------------------------
|
||||
|
||||
(* MARK_DEBUG="true" *) logic sample_req;
|
||||
(* MARK_DEBUG="true" *) logic sample_req_sync1;
|
||||
(* MARK_DEBUG="true" *) logic sample_req_sync2;
|
||||
(* MARK_DEBUG="true" *) logic sample_req_sync3;
|
||||
|
||||
(* MARK_DEBUG="true" *) logic sample_done;
|
||||
(* MARK_DEBUG="true" *) logic sample_done_sync1;
|
||||
(* MARK_DEBUG="true" *) logic sample_done_sync2;
|
||||
(* MARK_DEBUG="true" *) logic sample_done_sync3;
|
||||
|
||||
(* MARK_DEBUG="true" *) logic pulse;
|
||||
(* MARK_DEBUG="true" *) logic [DAC_DATA_WIDTH-1:0] pulse_height_out;
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Simple DAC -> ADC test source
|
||||
//
|
||||
// generator output is directly connected to sampler input
|
||||
// with width truncation:
|
||||
//
|
||||
// pulse_height_out[13:0] -> data_in[11:0]
|
||||
//------------------------------------------------------------
|
||||
(* MARK_DEBUG="true" *) logic [ADC_DATA_WIDTH-1:0] data_in;
|
||||
(* MARK_DEBUG="true" *) logic out_of_range;
|
||||
|
||||
assign data_in = pulse_height_out[ADC_DATA_WIDTH-1:0];
|
||||
assign out_of_range = 1'b0;
|
||||
|
||||
//------------------------------------------------------------
|
||||
// DAC -> ADC CDC
|
||||
//------------------------------------------------------------
|
||||
always_ff @(posedge adc_clk_in or posedge adc_rst) begin
|
||||
if (adc_rst) begin
|
||||
sample_req <= 1'b0;
|
||||
sample_req_sync2 <= 1'b0;
|
||||
sample_req_sync3 <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
sample_req_sync2 <= sample_req_sync1;
|
||||
sample_req_sync3 <= sample_req_sync2;
|
||||
sample_req <= sample_req_sync3;
|
||||
end
|
||||
end
|
||||
|
||||
//------------------------------------------------------------
|
||||
// ADC -> DAC CDC
|
||||
//------------------------------------------------------------
|
||||
always_ff @(posedge dac_clk_in or posedge dac_rst) begin
|
||||
if (dac_rst) begin
|
||||
sample_done <= 1'b0;
|
||||
sample_done_sync2 <= 1'b0;
|
||||
sample_done_sync3 <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
sample_done_sync2 <= sample_done_sync1;
|
||||
sample_done_sync3 <= sample_done_sync2;
|
||||
sample_done <= sample_done_sync3;
|
||||
end
|
||||
end
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Generator
|
||||
//------------------------------------------------------------
|
||||
generator #(
|
||||
.DATA_WIDTH(DAC_DATA_WIDTH)
|
||||
) generator_inst (
|
||||
.clk_in(dac_clk_in),
|
||||
.rst(dac_rst),
|
||||
.start(dac_start),
|
||||
|
||||
.pulse_width(pulse_width),
|
||||
.pulse_period(pulse_period),
|
||||
.pulse_height(pulse_height),
|
||||
.pulse_num(pulse_num),
|
||||
|
||||
.sample_done(sample_done),
|
||||
|
||||
.pulse(pulse),
|
||||
.pulse_height_out(pulse_height_out),
|
||||
.sample_req(sample_req_sync1)
|
||||
);
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Sampler
|
||||
//------------------------------------------------------------
|
||||
sampler #(
|
||||
.DATA_WIDTH(ADC_DATA_WIDTH),
|
||||
.PACK_FACTOR(PACK_FACTOR),
|
||||
.PROCESS_MODE(PROCESS_MODE)
|
||||
) sampler_inst (
|
||||
.clk_in(adc_clk_in),
|
||||
.rst(adc_rst),
|
||||
|
||||
.data_in(data_in),
|
||||
.out_of_range(out_of_range),
|
||||
|
||||
.smp_num(smp_num),
|
||||
.sample_req(sample_req),
|
||||
|
||||
.m_axis_tdata(m_axis_tdata),
|
||||
.m_axis_tvalid(m_axis_tvalid),
|
||||
.sample_done(sample_done_sync1)
|
||||
);
|
||||
|
||||
endmodule
|
||||
169
designs/adc_dac_synchoronizer/tb_sync_top.sv
Normal file
169
designs/adc_dac_synchoronizer/tb_sync_top.sv
Normal file
@ -0,0 +1,169 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module tb_top;
|
||||
|
||||
localparam DAC_DATA_WIDTH = 14;
|
||||
localparam ADC_DATA_WIDTH = 12;
|
||||
localparam PACK_FACTOR = 1;
|
||||
localparam PROCESS_MODE = 0;
|
||||
|
||||
//------------------------------------------------------------
|
||||
// clocks / reset
|
||||
//------------------------------------------------------------
|
||||
logic adc_clk_in;
|
||||
logic adc_rst;
|
||||
|
||||
logic dac_clk_in;
|
||||
logic dac_rst;
|
||||
|
||||
//------------------------------------------------------------
|
||||
// control
|
||||
//------------------------------------------------------------
|
||||
logic dac_start;
|
||||
|
||||
logic [31:0] pulse_width;
|
||||
logic [31:0] pulse_period;
|
||||
logic [DAC_DATA_WIDTH-1:0] pulse_height;
|
||||
logic [15:0] pulse_num;
|
||||
logic [31:0] smp_num;
|
||||
|
||||
//------------------------------------------------------------
|
||||
// outputs
|
||||
//------------------------------------------------------------
|
||||
logic [ADC_DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata;
|
||||
logic m_axis_tvalid;
|
||||
|
||||
integer valid_count;
|
||||
|
||||
//------------------------------------------------------------
|
||||
// DUT
|
||||
//------------------------------------------------------------
|
||||
sync_top #(
|
||||
.DAC_DATA_WIDTH(DAC_DATA_WIDTH),
|
||||
.ADC_DATA_WIDTH(ADC_DATA_WIDTH),
|
||||
.PACK_FACTOR(PACK_FACTOR),
|
||||
.PROCESS_MODE(PROCESS_MODE)
|
||||
) dut (
|
||||
.adc_clk_in(adc_clk_in),
|
||||
.adc_rst(adc_rst),
|
||||
|
||||
.dac_clk_in(dac_clk_in),
|
||||
.dac_rst(dac_rst),
|
||||
|
||||
.dac_start(dac_start),
|
||||
|
||||
.pulse_width(pulse_width),
|
||||
.pulse_period(pulse_period),
|
||||
.pulse_height(pulse_height),
|
||||
.pulse_num(pulse_num),
|
||||
.smp_num(smp_num),
|
||||
|
||||
.m_axis_tdata(m_axis_tdata),
|
||||
.m_axis_tvalid(m_axis_tvalid)
|
||||
);
|
||||
|
||||
//------------------------------------------------------------
|
||||
// ADC clock
|
||||
//------------------------------------------------------------
|
||||
initial begin
|
||||
adc_clk_in = 1'b0;
|
||||
forever #5 adc_clk_in = ~adc_clk_in; // 100 MHz
|
||||
end
|
||||
|
||||
//------------------------------------------------------------
|
||||
// DAC clock
|
||||
//------------------------------------------------------------
|
||||
initial begin
|
||||
dac_clk_in = 1'b0;
|
||||
forever #8 dac_clk_in = ~dac_clk_in; // slower domain
|
||||
end
|
||||
|
||||
//------------------------------------------------------------
|
||||
// monitor output stream
|
||||
//------------------------------------------------------------
|
||||
always @(posedge adc_clk_in) begin
|
||||
if (m_axis_tvalid) begin
|
||||
valid_count = valid_count + 1;
|
||||
|
||||
$display("[%0t] VALID: data=%0d",
|
||||
$time,
|
||||
m_axis_tdata);
|
||||
end
|
||||
end
|
||||
|
||||
//------------------------------------------------------------
|
||||
// test
|
||||
//------------------------------------------------------------
|
||||
initial begin
|
||||
|
||||
adc_rst = 1'b1;
|
||||
dac_rst = 1'b1;
|
||||
|
||||
dac_start = 1'b0;
|
||||
|
||||
pulse_width = 0;
|
||||
pulse_period = 0;
|
||||
pulse_height = 0;
|
||||
pulse_num = 0;
|
||||
smp_num = 0;
|
||||
|
||||
valid_count = 0;
|
||||
|
||||
//--------------------------------------------------------
|
||||
// reset
|
||||
//--------------------------------------------------------
|
||||
repeat (10) @(posedge adc_clk_in);
|
||||
repeat (10) @(posedge dac_clk_in);
|
||||
|
||||
adc_rst = 1'b0;
|
||||
dac_rst = 1'b0;
|
||||
|
||||
repeat (5) @(posedge dac_clk_in);
|
||||
|
||||
//--------------------------------------------------------
|
||||
// config
|
||||
//--------------------------------------------------------
|
||||
pulse_width = 32'd3;
|
||||
pulse_period = 32'd8;
|
||||
pulse_height = 14'd200;
|
||||
pulse_num = 16'd4;
|
||||
smp_num = 32'd8;
|
||||
|
||||
//--------------------------------------------------------
|
||||
// start
|
||||
//--------------------------------------------------------
|
||||
@(posedge dac_clk_in);
|
||||
dac_start = 1'b1;
|
||||
|
||||
@(posedge dac_clk_in);
|
||||
dac_start = 1'b0;
|
||||
|
||||
$display("==================================");
|
||||
$display("TEST START");
|
||||
$display("==================================");
|
||||
|
||||
//--------------------------------------------------------
|
||||
// wait
|
||||
//--------------------------------------------------------
|
||||
repeat (600) @(posedge adc_clk_in);
|
||||
|
||||
//--------------------------------------------------------
|
||||
// check
|
||||
//--------------------------------------------------------
|
||||
if (valid_count > 0) begin
|
||||
$display("==================================");
|
||||
$display("TEST PASSED");
|
||||
$display("valid_count = %0d", valid_count);
|
||||
$display("==================================");
|
||||
end
|
||||
else begin
|
||||
$display("==================================");
|
||||
$display("TEST FAILED");
|
||||
$display("No valid output detected");
|
||||
$display("==================================");
|
||||
end
|
||||
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@ -1,7 +0,0 @@
|
||||
# Тестовый проект Eth + CTRL
|
||||
Проект состоит из AXIS Ethernet и контроллера. Для тестирования сделано три разных частотных домена: ethernet 125MHz, DAC 130MHz, ADC 65MHz для тестирования сихронизации. Есть ILA на все выходы контроллера и на шину AXIS eth -> ctrl. Для отправки пакетов используйте скрипт ```console.py --debug```.
|
||||
|
||||
## Сборка
|
||||
```make all``` - собрать все до битстрима
|
||||
|
||||
```make vivado``` - открыть проект в Vivado
|
||||
@ -1,147 +0,0 @@
|
||||
set_clock_groups -name ASYNC_UDP_CTRL -asynchronous -group [get_clocks rgmii_rxc] -group [get_clocks clk_out1_clk_wiz_ctrl_inst] -group [get_clocks clk_out2_clk_wiz_ctrl_inst]
|
||||
|
||||
|
||||
|
||||
|
||||
create_debug_core u_ila_0 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
|
||||
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/clk]
|
||||
connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out2]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe0]
|
||||
connect_debug_port u_ila_0/probe0 [get_nets [list {adc_pulse_period_dbg[0]} {adc_pulse_period_dbg[1]} {adc_pulse_period_dbg[2]} {adc_pulse_period_dbg[3]} {adc_pulse_period_dbg[4]} {adc_pulse_period_dbg[5]} {adc_pulse_period_dbg[6]} {adc_pulse_period_dbg[7]} {adc_pulse_period_dbg[8]} {adc_pulse_period_dbg[9]} {adc_pulse_period_dbg[10]} {adc_pulse_period_dbg[11]} {adc_pulse_period_dbg[12]} {adc_pulse_period_dbg[13]} {adc_pulse_period_dbg[14]} {adc_pulse_period_dbg[15]} {adc_pulse_period_dbg[16]} {adc_pulse_period_dbg[17]} {adc_pulse_period_dbg[18]} {adc_pulse_period_dbg[19]} {adc_pulse_period_dbg[20]} {adc_pulse_period_dbg[21]} {adc_pulse_period_dbg[22]} {adc_pulse_period_dbg[23]} {adc_pulse_period_dbg[24]} {adc_pulse_period_dbg[25]} {adc_pulse_period_dbg[26]} {adc_pulse_period_dbg[27]} {adc_pulse_period_dbg[28]} {adc_pulse_period_dbg[29]} {adc_pulse_period_dbg[30]} {adc_pulse_period_dbg[31]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe1]
|
||||
connect_debug_port u_ila_0/probe1 [get_nets [list {finish_cnt[0]} {finish_cnt[1]} {finish_cnt[2]} {finish_cnt[3]} {finish_cnt[4]} {finish_cnt[5]} {finish_cnt[6]} {finish_cnt[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe2]
|
||||
connect_debug_port u_ila_0/probe2 [get_nets [list {adc_pulse_num_dbg[0]} {adc_pulse_num_dbg[1]} {adc_pulse_num_dbg[2]} {adc_pulse_num_dbg[3]} {adc_pulse_num_dbg[4]} {adc_pulse_num_dbg[5]} {adc_pulse_num_dbg[6]} {adc_pulse_num_dbg[7]} {adc_pulse_num_dbg[8]} {adc_pulse_num_dbg[9]} {adc_pulse_num_dbg[10]} {adc_pulse_num_dbg[11]} {adc_pulse_num_dbg[12]} {adc_pulse_num_dbg[13]} {adc_pulse_num_dbg[14]} {adc_pulse_num_dbg[15]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe3]
|
||||
connect_debug_port u_ila_0/probe3 [get_nets [list adc_rst_dbg]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list adc_start_dbg]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list finish_dbg]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
|
||||
connect_debug_port u_ila_0/probe6 [get_nets [list finish_pending]]
|
||||
create_debug_core u_ila_1 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1]
|
||||
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/clk]
|
||||
connect_debug_port u_ila_1/clk [get_nets [list rgmii_rxc_IBUF_BUFG]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
|
||||
set_property port_width 2 [get_debug_ports u_ila_1/probe0]
|
||||
connect_debug_port u_ila_1/probe0 [get_nets [list {axis_mac0/rx_state[0]} {axis_mac0/rx_state[1]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe1]
|
||||
connect_debug_port u_ila_1/probe1 [get_nets [list {axis_mac0/udp_rec_data_length[0]} {axis_mac0/udp_rec_data_length[1]} {axis_mac0/udp_rec_data_length[2]} {axis_mac0/udp_rec_data_length[3]} {axis_mac0/udp_rec_data_length[4]} {axis_mac0/udp_rec_data_length[5]} {axis_mac0/udp_rec_data_length[6]} {axis_mac0/udp_rec_data_length[7]} {axis_mac0/udp_rec_data_length[8]} {axis_mac0/udp_rec_data_length[9]} {axis_mac0/udp_rec_data_length[10]} {axis_mac0/udp_rec_data_length[11]} {axis_mac0/udp_rec_data_length[12]} {axis_mac0/udp_rec_data_length[13]} {axis_mac0/udp_rec_data_length[14]} {axis_mac0/udp_rec_data_length[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2]
|
||||
set_property port_width 96 [get_debug_ports u_ila_1/probe2]
|
||||
connect_debug_port u_ila_1/probe2 [get_nets [list {udp_ctrl_inst/cfg_bus_eth[0]} {udp_ctrl_inst/cfg_bus_eth[1]} {udp_ctrl_inst/cfg_bus_eth[2]} {udp_ctrl_inst/cfg_bus_eth[3]} {udp_ctrl_inst/cfg_bus_eth[4]} {udp_ctrl_inst/cfg_bus_eth[5]} {udp_ctrl_inst/cfg_bus_eth[6]} {udp_ctrl_inst/cfg_bus_eth[7]} {udp_ctrl_inst/cfg_bus_eth[8]} {udp_ctrl_inst/cfg_bus_eth[9]} {udp_ctrl_inst/cfg_bus_eth[10]} {udp_ctrl_inst/cfg_bus_eth[11]} {udp_ctrl_inst/cfg_bus_eth[12]} {udp_ctrl_inst/cfg_bus_eth[13]} {udp_ctrl_inst/cfg_bus_eth[14]} {udp_ctrl_inst/cfg_bus_eth[15]} {udp_ctrl_inst/cfg_bus_eth[16]} {udp_ctrl_inst/cfg_bus_eth[17]} {udp_ctrl_inst/cfg_bus_eth[18]} {udp_ctrl_inst/cfg_bus_eth[19]} {udp_ctrl_inst/cfg_bus_eth[20]} {udp_ctrl_inst/cfg_bus_eth[21]} {udp_ctrl_inst/cfg_bus_eth[22]} {udp_ctrl_inst/cfg_bus_eth[23]} {udp_ctrl_inst/cfg_bus_eth[24]} {udp_ctrl_inst/cfg_bus_eth[25]} {udp_ctrl_inst/cfg_bus_eth[26]} {udp_ctrl_inst/cfg_bus_eth[27]} {udp_ctrl_inst/cfg_bus_eth[28]} {udp_ctrl_inst/cfg_bus_eth[29]} {udp_ctrl_inst/cfg_bus_eth[30]} {udp_ctrl_inst/cfg_bus_eth[31]} {udp_ctrl_inst/cfg_bus_eth[32]} {udp_ctrl_inst/cfg_bus_eth[33]} {udp_ctrl_inst/cfg_bus_eth[34]} {udp_ctrl_inst/cfg_bus_eth[35]} {udp_ctrl_inst/cfg_bus_eth[36]} {udp_ctrl_inst/cfg_bus_eth[37]} {udp_ctrl_inst/cfg_bus_eth[38]} {udp_ctrl_inst/cfg_bus_eth[39]} {udp_ctrl_inst/cfg_bus_eth[40]} {udp_ctrl_inst/cfg_bus_eth[41]} {udp_ctrl_inst/cfg_bus_eth[42]} {udp_ctrl_inst/cfg_bus_eth[43]} {udp_ctrl_inst/cfg_bus_eth[44]} {udp_ctrl_inst/cfg_bus_eth[45]} {udp_ctrl_inst/cfg_bus_eth[46]} {udp_ctrl_inst/cfg_bus_eth[47]} {udp_ctrl_inst/cfg_bus_eth[48]} {udp_ctrl_inst/cfg_bus_eth[49]} {udp_ctrl_inst/cfg_bus_eth[50]} {udp_ctrl_inst/cfg_bus_eth[51]} {udp_ctrl_inst/cfg_bus_eth[52]} {udp_ctrl_inst/cfg_bus_eth[53]} {udp_ctrl_inst/cfg_bus_eth[54]} {udp_ctrl_inst/cfg_bus_eth[55]} {udp_ctrl_inst/cfg_bus_eth[56]} {udp_ctrl_inst/cfg_bus_eth[57]} {udp_ctrl_inst/cfg_bus_eth[58]} {udp_ctrl_inst/cfg_bus_eth[59]} {udp_ctrl_inst/cfg_bus_eth[60]} {udp_ctrl_inst/cfg_bus_eth[61]} {udp_ctrl_inst/cfg_bus_eth[62]} {udp_ctrl_inst/cfg_bus_eth[63]} {udp_ctrl_inst/cfg_bus_eth[64]} {udp_ctrl_inst/cfg_bus_eth[65]} {udp_ctrl_inst/cfg_bus_eth[66]} {udp_ctrl_inst/cfg_bus_eth[67]} {udp_ctrl_inst/cfg_bus_eth[68]} {udp_ctrl_inst/cfg_bus_eth[69]} {udp_ctrl_inst/cfg_bus_eth[70]} {udp_ctrl_inst/cfg_bus_eth[71]} {udp_ctrl_inst/cfg_bus_eth[72]} {udp_ctrl_inst/cfg_bus_eth[73]} {udp_ctrl_inst/cfg_bus_eth[74]} {udp_ctrl_inst/cfg_bus_eth[75]} {udp_ctrl_inst/cfg_bus_eth[76]} {udp_ctrl_inst/cfg_bus_eth[77]} {udp_ctrl_inst/cfg_bus_eth[78]} {udp_ctrl_inst/cfg_bus_eth[79]} {udp_ctrl_inst/cfg_bus_eth[80]} {udp_ctrl_inst/cfg_bus_eth[81]} {udp_ctrl_inst/cfg_bus_eth[82]} {udp_ctrl_inst/cfg_bus_eth[83]} {udp_ctrl_inst/cfg_bus_eth[84]} {udp_ctrl_inst/cfg_bus_eth[85]} {udp_ctrl_inst/cfg_bus_eth[86]} {udp_ctrl_inst/cfg_bus_eth[87]} {udp_ctrl_inst/cfg_bus_eth[88]} {udp_ctrl_inst/cfg_bus_eth[89]} {udp_ctrl_inst/cfg_bus_eth[90]} {udp_ctrl_inst/cfg_bus_eth[91]} {udp_ctrl_inst/cfg_bus_eth[92]} {udp_ctrl_inst/cfg_bus_eth[93]} {udp_ctrl_inst/cfg_bus_eth[94]} {udp_ctrl_inst/cfg_bus_eth[95]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe3]
|
||||
connect_debug_port u_ila_1/probe3 [get_nets [list {axis_mac0/rx_payload_len[0]} {axis_mac0/rx_payload_len[1]} {axis_mac0/rx_payload_len[2]} {axis_mac0/rx_payload_len[3]} {axis_mac0/rx_payload_len[4]} {axis_mac0/rx_payload_len[5]} {axis_mac0/rx_payload_len[6]} {axis_mac0/rx_payload_len[7]} {axis_mac0/rx_payload_len[8]} {axis_mac0/rx_payload_len[9]} {axis_mac0/rx_payload_len[10]} {axis_mac0/rx_payload_len[11]} {axis_mac0/rx_payload_len[12]} {axis_mac0/rx_payload_len[13]} {axis_mac0/rx_payload_len[14]} {axis_mac0/rx_payload_len[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4]
|
||||
set_property port_width 8 [get_debug_ports u_ila_1/probe4]
|
||||
connect_debug_port u_ila_1/probe4 [get_nets [list {m_axis_rx_tdata[0]} {m_axis_rx_tdata[1]} {m_axis_rx_tdata[2]} {m_axis_rx_tdata[3]} {m_axis_rx_tdata[4]} {m_axis_rx_tdata[5]} {m_axis_rx_tdata[6]} {m_axis_rx_tdata[7]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5]
|
||||
set_property port_width 3 [get_debug_ports u_ila_1/probe5]
|
||||
connect_debug_port u_ila_1/probe5 [get_nets [list {udp_ctrl_inst/eth_state[0]} {udp_ctrl_inst/eth_state[1]} {udp_ctrl_inst/eth_state[2]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe6]
|
||||
connect_debug_port u_ila_1/probe6 [get_nets [list axis_mac0/arp_found]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe7]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe7]
|
||||
connect_debug_port u_ila_1/probe7 [get_nets [list udp_ctrl_inst/axis_hs]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe8]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe8]
|
||||
connect_debug_port u_ila_1/probe8 [get_nets [list udp_ctrl_inst/busy_flag_eth]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe9]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe9]
|
||||
connect_debug_port u_ila_1/probe9 [get_nets [list axis_mac0/m_axis_rx_tlast]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe10]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe10]
|
||||
connect_debug_port u_ila_1/probe10 [get_nets [list m_axis_rx_tlast]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe11]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe11]
|
||||
connect_debug_port u_ila_1/probe11 [get_nets [list axis_mac0/m_axis_rx_tready]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe12]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe12]
|
||||
connect_debug_port u_ila_1/probe12 [get_nets [list m_axis_rx_tready]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe13]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe13]
|
||||
connect_debug_port u_ila_1/probe13 [get_nets [list axis_mac0/req_ready]]
|
||||
create_debug_core u_ila_2 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2]
|
||||
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_2]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_2]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_2]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2]
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/clk]
|
||||
connect_debug_port u_ila_2/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out1]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe0]
|
||||
set_property port_width 12 [get_debug_ports u_ila_2/probe0]
|
||||
connect_debug_port u_ila_2/probe0 [get_nets [list {dac_pulse_height_dbg[0]} {dac_pulse_height_dbg[1]} {dac_pulse_height_dbg[2]} {dac_pulse_height_dbg[3]} {dac_pulse_height_dbg[4]} {dac_pulse_height_dbg[5]} {dac_pulse_height_dbg[6]} {dac_pulse_height_dbg[7]} {dac_pulse_height_dbg[8]} {dac_pulse_height_dbg[9]} {dac_pulse_height_dbg[10]} {dac_pulse_height_dbg[11]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe1]
|
||||
set_property port_width 16 [get_debug_ports u_ila_2/probe1]
|
||||
connect_debug_port u_ila_2/probe1 [get_nets [list {dac_pulse_num_dbg[0]} {dac_pulse_num_dbg[1]} {dac_pulse_num_dbg[2]} {dac_pulse_num_dbg[3]} {dac_pulse_num_dbg[4]} {dac_pulse_num_dbg[5]} {dac_pulse_num_dbg[6]} {dac_pulse_num_dbg[7]} {dac_pulse_num_dbg[8]} {dac_pulse_num_dbg[9]} {dac_pulse_num_dbg[10]} {dac_pulse_num_dbg[11]} {dac_pulse_num_dbg[12]} {dac_pulse_num_dbg[13]} {dac_pulse_num_dbg[14]} {dac_pulse_num_dbg[15]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe2]
|
||||
set_property port_width 32 [get_debug_ports u_ila_2/probe2]
|
||||
connect_debug_port u_ila_2/probe2 [get_nets [list {dac_pulse_period_dbg[0]} {dac_pulse_period_dbg[1]} {dac_pulse_period_dbg[2]} {dac_pulse_period_dbg[3]} {dac_pulse_period_dbg[4]} {dac_pulse_period_dbg[5]} {dac_pulse_period_dbg[6]} {dac_pulse_period_dbg[7]} {dac_pulse_period_dbg[8]} {dac_pulse_period_dbg[9]} {dac_pulse_period_dbg[10]} {dac_pulse_period_dbg[11]} {dac_pulse_period_dbg[12]} {dac_pulse_period_dbg[13]} {dac_pulse_period_dbg[14]} {dac_pulse_period_dbg[15]} {dac_pulse_period_dbg[16]} {dac_pulse_period_dbg[17]} {dac_pulse_period_dbg[18]} {dac_pulse_period_dbg[19]} {dac_pulse_period_dbg[20]} {dac_pulse_period_dbg[21]} {dac_pulse_period_dbg[22]} {dac_pulse_period_dbg[23]} {dac_pulse_period_dbg[24]} {dac_pulse_period_dbg[25]} {dac_pulse_period_dbg[26]} {dac_pulse_period_dbg[27]} {dac_pulse_period_dbg[28]} {dac_pulse_period_dbg[29]} {dac_pulse_period_dbg[30]} {dac_pulse_period_dbg[31]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe3]
|
||||
set_property port_width 32 [get_debug_ports u_ila_2/probe3]
|
||||
connect_debug_port u_ila_2/probe3 [get_nets [list {dac_pulse_width_dbg[0]} {dac_pulse_width_dbg[1]} {dac_pulse_width_dbg[2]} {dac_pulse_width_dbg[3]} {dac_pulse_width_dbg[4]} {dac_pulse_width_dbg[5]} {dac_pulse_width_dbg[6]} {dac_pulse_width_dbg[7]} {dac_pulse_width_dbg[8]} {dac_pulse_width_dbg[9]} {dac_pulse_width_dbg[10]} {dac_pulse_width_dbg[11]} {dac_pulse_width_dbg[12]} {dac_pulse_width_dbg[13]} {dac_pulse_width_dbg[14]} {dac_pulse_width_dbg[15]} {dac_pulse_width_dbg[16]} {dac_pulse_width_dbg[17]} {dac_pulse_width_dbg[18]} {dac_pulse_width_dbg[19]} {dac_pulse_width_dbg[20]} {dac_pulse_width_dbg[21]} {dac_pulse_width_dbg[22]} {dac_pulse_width_dbg[23]} {dac_pulse_width_dbg[24]} {dac_pulse_width_dbg[25]} {dac_pulse_width_dbg[26]} {dac_pulse_width_dbg[27]} {dac_pulse_width_dbg[28]} {dac_pulse_width_dbg[29]} {dac_pulse_width_dbg[30]} {dac_pulse_width_dbg[31]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe4]
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/probe4]
|
||||
connect_debug_port u_ila_2/probe4 [get_nets [list dac_rst_dbg]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe5]
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/probe5]
|
||||
connect_debug_port u_ila_2/probe5 [get_nets [list dac_start_dbg]]
|
||||
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
|
||||
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
|
||||
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
|
||||
connect_debug_port dbg_hub/clk [get_nets dac_clk]
|
||||
@ -1,298 +0,0 @@
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module eth_ctrl_debug_top #(
|
||||
parameter int unsigned DAC_DATA_WIDTH = 12
|
||||
)(
|
||||
input sys_clk_p,
|
||||
input sys_clk_n,
|
||||
input rst_n,
|
||||
|
||||
output [3:0] led,
|
||||
|
||||
output e_reset,
|
||||
output e_mdc,
|
||||
inout e_mdio,
|
||||
|
||||
output [3:0] rgmii_txd,
|
||||
output rgmii_txctl,
|
||||
output rgmii_txc,
|
||||
input [3:0] rgmii_rxd,
|
||||
input rgmii_rxctl,
|
||||
input rgmii_rxc
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Internal GMII-side signals
|
||||
// -------------------------------------------------------------------------
|
||||
wire [7:0] gmii_txd;
|
||||
wire gmii_tx_en;
|
||||
wire gmii_tx_er;
|
||||
wire gmii_tx_clk;
|
||||
wire gmii_crs;
|
||||
wire gmii_col;
|
||||
wire [7:0] gmii_rxd_i;
|
||||
wire gmii_rx_dv;
|
||||
wire gmii_rx_er;
|
||||
wire gmii_rx_clk;
|
||||
|
||||
wire [31:0] pack_total_len;
|
||||
|
||||
wire e_rx_dv;
|
||||
wire [7:0] e_rxd;
|
||||
wire e_tx_en;
|
||||
wire [7:0] e_txd;
|
||||
wire e_rst_n;
|
||||
wire sys_clk;
|
||||
|
||||
wire duplex_mode;
|
||||
|
||||
assign duplex_mode = 1'b1;
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// System clock buffer (200 MHz differential input)
|
||||
// -------------------------------------------------------------------------
|
||||
IBUFDS sys_clk_ibufgds (
|
||||
.O (sys_clk),
|
||||
.I (sys_clk_p),
|
||||
.IB (sys_clk_n)
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// IDELAYCTRL
|
||||
// -------------------------------------------------------------------------
|
||||
(* IODELAY_GROUP = "rgmii_idelay_group" *)
|
||||
IDELAYCTRL IDELAYCTRL_inst (
|
||||
.RDY (),
|
||||
.REFCLK (sys_clk),
|
||||
.RST (1'b0)
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Generated clocks for controller
|
||||
// Need to create this IP in Vivado:
|
||||
// input : 200 MHz
|
||||
// output0: 130 MHz
|
||||
// output1: 65 MHz
|
||||
// -------------------------------------------------------------------------
|
||||
wire dac_clk;
|
||||
wire adc_clk;
|
||||
wire clk_wiz_locked;
|
||||
|
||||
clk_wiz_ctrl_inst clk_wiz_ctrl_inst (
|
||||
.clk_in1 (sys_clk),
|
||||
.reset (~rst_n),
|
||||
.clk_out1 (dac_clk), // 130 MHz
|
||||
.clk_out2 (adc_clk), // 65 MHz
|
||||
.locked (clk_wiz_locked)
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// GMII <-> RGMII conversion
|
||||
// -------------------------------------------------------------------------
|
||||
util_gmii_to_rgmii util_gmii_to_rgmii_m0 (
|
||||
.reset (1'b0),
|
||||
.rgmii_td (rgmii_txd),
|
||||
.rgmii_tx_ctl (rgmii_txctl),
|
||||
.rgmii_txc (rgmii_txc),
|
||||
.rgmii_rd (rgmii_rxd),
|
||||
.rgmii_rx_ctl (rgmii_rxctl),
|
||||
.gmii_rx_clk (gmii_rx_clk),
|
||||
.gmii_txd (e_txd),
|
||||
.gmii_tx_en (e_tx_en),
|
||||
.gmii_tx_er (1'b0),
|
||||
.gmii_tx_clk (gmii_tx_clk),
|
||||
.gmii_crs (gmii_crs),
|
||||
.gmii_col (gmii_col),
|
||||
.gmii_rxd (gmii_rxd_i),
|
||||
.rgmii_rxc (rgmii_rxc),
|
||||
.gmii_rx_dv (gmii_rx_dv),
|
||||
.gmii_rx_er (gmii_rx_er),
|
||||
.speed_selection (2'b10),
|
||||
.duplex_mode (duplex_mode)
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// GMII arbitration / adaptation
|
||||
// -------------------------------------------------------------------------
|
||||
gmii_arbi arbi_inst (
|
||||
.clk (gmii_tx_clk),
|
||||
.rst_n (rst_n),
|
||||
.speed (2'b10),
|
||||
.link (1'b1),
|
||||
.pack_total_len (pack_total_len),
|
||||
.e_rst_n (e_rst_n),
|
||||
.gmii_rx_dv (gmii_rx_dv),
|
||||
.gmii_rxd (gmii_rxd_i),
|
||||
.gmii_tx_en (gmii_tx_en),
|
||||
.gmii_txd (gmii_txd),
|
||||
.e_rx_dv (e_rx_dv),
|
||||
.e_rxd (e_rxd),
|
||||
.e_tx_en (e_tx_en),
|
||||
.e_txd (e_txd)
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// axis_mac interface
|
||||
// RX stream from Ethernet goes into controller
|
||||
// TX stream is unused for now
|
||||
// -------------------------------------------------------------------------
|
||||
wire req_ready;
|
||||
|
||||
reg send_req;
|
||||
reg [15:0] data_length;
|
||||
|
||||
reg [7:0] s_axis_tx_tdata;
|
||||
reg s_axis_tx_tvalid;
|
||||
wire s_axis_tx_tready;
|
||||
reg s_axis_tx_tlast;
|
||||
|
||||
(* MARK_DEBUG="true" *) wire [7:0] m_axis_rx_tdata;
|
||||
(* MARK_DEBUG="true" *) wire m_axis_rx_tvalid;
|
||||
(* MARK_DEBUG="true" *) wire m_axis_rx_tlast;
|
||||
(* MARK_DEBUG="true" *) wire m_axis_rx_tready;
|
||||
|
||||
// Always ready to accept RX payload bytes
|
||||
assign m_axis_rx_tready = 1'b1;
|
||||
|
||||
// TX disabled
|
||||
always @(*) begin
|
||||
send_req = 1'b0;
|
||||
data_length = 16'd0;
|
||||
s_axis_tx_tdata = 8'd0;
|
||||
s_axis_tx_tvalid= 1'b0;
|
||||
s_axis_tx_tlast = 1'b0;
|
||||
end
|
||||
|
||||
axis_mac axis_mac0 (
|
||||
.gmii_tx_clk (gmii_tx_clk),
|
||||
.gmii_rx_clk (gmii_rx_clk),
|
||||
.rst_n (e_rst_n),
|
||||
|
||||
.gmii_rx_dv (e_rx_dv),
|
||||
.gmii_rxd (e_rxd),
|
||||
.gmii_tx_en (gmii_tx_en),
|
||||
.gmii_txd (gmii_txd),
|
||||
|
||||
.send_req (send_req),
|
||||
.data_length (data_length),
|
||||
.req_ready (req_ready),
|
||||
|
||||
.s_axis_tx_tdata (s_axis_tx_tdata),
|
||||
.s_axis_tx_tvalid (s_axis_tx_tvalid),
|
||||
.s_axis_tx_tready (s_axis_tx_tready),
|
||||
.s_axis_tx_tlast (s_axis_tx_tlast),
|
||||
|
||||
.m_axis_rx_tdata (m_axis_rx_tdata),
|
||||
.m_axis_rx_tvalid (m_axis_rx_tvalid),
|
||||
.m_axis_rx_tready (m_axis_rx_tready),
|
||||
.m_axis_rx_tlast (m_axis_rx_tlast)
|
||||
);
|
||||
|
||||
// PHY reset helper from your original example
|
||||
reset reset_m0 (
|
||||
.clk (sys_clk),
|
||||
.key1 (rst_n),
|
||||
.rst_n (e_reset)
|
||||
);
|
||||
|
||||
// MDIO lines are not driven here yet
|
||||
assign e_mdc = 1'b0;
|
||||
assign e_mdio = 1'bz;
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Controller reset
|
||||
// Use both external reset and clk_wiz lock
|
||||
// -------------------------------------------------------------------------
|
||||
wire ctrl_rst_n = rst_n & clk_wiz_locked;
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Debug finish generator
|
||||
//
|
||||
// After each adc_start pulse generates one finish pulse after some delay.
|
||||
// This is just for first bring-up so the controller can leave busy state
|
||||
// If you don't want this, replace with:
|
||||
// wire finish_dbg = 1'b0;
|
||||
// -------------------------------------------------------------------------
|
||||
(* MARK_DEBUG="true" *) logic finish_dbg;
|
||||
(* MARK_DEBUG="true" *) logic [7:0] finish_cnt;
|
||||
(* MARK_DEBUG="true" *) logic finish_pending;
|
||||
|
||||
// Controller outputs to debug
|
||||
(* MARK_DEBUG="true" *) wire [31:0] dac_pulse_width_dbg;
|
||||
(* MARK_DEBUG="true" *) wire [31:0] dac_pulse_period_dbg;
|
||||
(* MARK_DEBUG="true" *) wire [DAC_DATA_WIDTH-1:0] dac_pulse_height_dbg;
|
||||
(* MARK_DEBUG="true" *) wire [15:0] dac_pulse_num_dbg;
|
||||
|
||||
(* MARK_DEBUG="true" *) wire [31:0] adc_pulse_period_dbg;
|
||||
(* MARK_DEBUG="true" *) wire [15:0] adc_pulse_num_dbg;
|
||||
|
||||
(* MARK_DEBUG="true" *) wire dac_start_dbg;
|
||||
(* MARK_DEBUG="true" *) wire adc_start_dbg;
|
||||
(* MARK_DEBUG="true" *) wire dac_rst_dbg;
|
||||
(* MARK_DEBUG="true" *) wire adc_rst_dbg;
|
||||
|
||||
always_ff @(posedge adc_clk or negedge ctrl_rst_n) begin
|
||||
if (!ctrl_rst_n) begin
|
||||
finish_dbg <= 1'b0;
|
||||
finish_cnt <= 8'd0;
|
||||
finish_pending <= 1'b0;
|
||||
end else begin
|
||||
finish_dbg <= 1'b0;
|
||||
|
||||
if (adc_start_dbg) begin
|
||||
finish_pending <= 1'b1;
|
||||
finish_cnt <= 8'd80;
|
||||
end else if (finish_pending) begin
|
||||
if (finish_cnt == 8'd0) begin
|
||||
finish_dbg <= 1'b1;
|
||||
finish_pending <= 1'b0;
|
||||
end else begin
|
||||
finish_cnt <= finish_cnt - 8'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Controller
|
||||
// ETH domain = gmii_rx_clk, because RX AXI master comes from axis_mac RX side
|
||||
// -------------------------------------------------------------------------
|
||||
control #(
|
||||
.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
|
||||
) udp_ctrl_inst (
|
||||
.eth_clk_in (gmii_rx_clk),
|
||||
.dac_clk_in (dac_clk),
|
||||
.adc_clk_in (adc_clk),
|
||||
.rst_n (ctrl_rst_n),
|
||||
|
||||
.s_axis_tdata (m_axis_rx_tdata),
|
||||
.s_axis_tvalid (m_axis_rx_tvalid),
|
||||
.s_axis_tready (), // controller internally always ready in current version
|
||||
.s_axis_tlast (m_axis_rx_tlast),
|
||||
|
||||
.finish (finish_dbg),
|
||||
|
||||
.dac_pulse_width (dac_pulse_width_dbg),
|
||||
.dac_pulse_period (dac_pulse_period_dbg),
|
||||
.dac_pulse_height (dac_pulse_height_dbg),
|
||||
.dac_pulse_num (dac_pulse_num_dbg),
|
||||
|
||||
.adc_pulse_period (adc_pulse_period_dbg),
|
||||
.adc_pulse_num (adc_pulse_num_dbg),
|
||||
|
||||
.dac_start (dac_start_dbg),
|
||||
.adc_start (adc_start_dbg),
|
||||
|
||||
.dac_rst (dac_rst_dbg),
|
||||
.adc_rst (adc_rst_dbg)
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Simple LED status
|
||||
// -------------------------------------------------------------------------
|
||||
assign led[0] = clk_wiz_locked;
|
||||
assign led[1] = m_axis_rx_tvalid;
|
||||
assign led[2] = dac_start_dbg;
|
||||
assign led[3] = adc_rst_dbg;
|
||||
|
||||
endmodule
|
||||
@ -1,11 +0,0 @@
|
||||
# Тестовый проект Generator + ETH + CTRL
|
||||
Проект состоит из AXIS Ethernet, контроллера и генератора. Позволяет генерировать сигналы, задав параметры через Ethernet.
|
||||
## Сборка
|
||||
```make all``` - собрать все до битстрима
|
||||
|
||||
```make vivado``` - открыть проект в Vivado
|
||||
|
||||
## Управление
|
||||
Используйте software/console.py. Пример:
|
||||
|
||||
```python3 console.py --pulse_width 3_500_000 --pulse_period 20_000_000 --pulse_height 10000 --pulse_num 5500 --dac-bits 14```
|
||||
@ -1,117 +0,0 @@
|
||||
set_clock_groups -name ASYNC_UDP_CTRL -asynchronous -group [get_clocks rgmii_rxc] -group [get_clocks clk_out1_clk_wiz_ctrl_inst] -group [get_clocks clk_out2_clk_wiz_ctrl_inst]
|
||||
|
||||
|
||||
|
||||
|
||||
connect_debug_port u_ila_2/probe0 [get_nets [list {dac_pulse_height_dbg[0]} {dac_pulse_height_dbg[1]} {dac_pulse_height_dbg[2]} {dac_pulse_height_dbg[3]} {dac_pulse_height_dbg[4]} {dac_pulse_height_dbg[5]} {dac_pulse_height_dbg[6]} {dac_pulse_height_dbg[7]} {dac_pulse_height_dbg[8]} {dac_pulse_height_dbg[9]} {dac_pulse_height_dbg[10]} {dac_pulse_height_dbg[11]}]]
|
||||
connect_debug_port u_ila_2/probe1 [get_nets [list {dac_pulse_num_dbg[0]} {dac_pulse_num_dbg[1]} {dac_pulse_num_dbg[2]} {dac_pulse_num_dbg[3]} {dac_pulse_num_dbg[4]} {dac_pulse_num_dbg[5]} {dac_pulse_num_dbg[6]} {dac_pulse_num_dbg[7]} {dac_pulse_num_dbg[8]} {dac_pulse_num_dbg[9]} {dac_pulse_num_dbg[10]} {dac_pulse_num_dbg[11]} {dac_pulse_num_dbg[12]} {dac_pulse_num_dbg[13]} {dac_pulse_num_dbg[14]} {dac_pulse_num_dbg[15]}]]
|
||||
connect_debug_port u_ila_2/probe2 [get_nets [list {dac_pulse_period_dbg[0]} {dac_pulse_period_dbg[1]} {dac_pulse_period_dbg[2]} {dac_pulse_period_dbg[3]} {dac_pulse_period_dbg[4]} {dac_pulse_period_dbg[5]} {dac_pulse_period_dbg[6]} {dac_pulse_period_dbg[7]} {dac_pulse_period_dbg[8]} {dac_pulse_period_dbg[9]} {dac_pulse_period_dbg[10]} {dac_pulse_period_dbg[11]} {dac_pulse_period_dbg[12]} {dac_pulse_period_dbg[13]} {dac_pulse_period_dbg[14]} {dac_pulse_period_dbg[15]} {dac_pulse_period_dbg[16]} {dac_pulse_period_dbg[17]} {dac_pulse_period_dbg[18]} {dac_pulse_period_dbg[19]} {dac_pulse_period_dbg[20]} {dac_pulse_period_dbg[21]} {dac_pulse_period_dbg[22]} {dac_pulse_period_dbg[23]} {dac_pulse_period_dbg[24]} {dac_pulse_period_dbg[25]} {dac_pulse_period_dbg[26]} {dac_pulse_period_dbg[27]} {dac_pulse_period_dbg[28]} {dac_pulse_period_dbg[29]} {dac_pulse_period_dbg[30]} {dac_pulse_period_dbg[31]}]]
|
||||
connect_debug_port u_ila_2/probe3 [get_nets [list {dac_pulse_width_dbg[0]} {dac_pulse_width_dbg[1]} {dac_pulse_width_dbg[2]} {dac_pulse_width_dbg[3]} {dac_pulse_width_dbg[4]} {dac_pulse_width_dbg[5]} {dac_pulse_width_dbg[6]} {dac_pulse_width_dbg[7]} {dac_pulse_width_dbg[8]} {dac_pulse_width_dbg[9]} {dac_pulse_width_dbg[10]} {dac_pulse_width_dbg[11]} {dac_pulse_width_dbg[12]} {dac_pulse_width_dbg[13]} {dac_pulse_width_dbg[14]} {dac_pulse_width_dbg[15]} {dac_pulse_width_dbg[16]} {dac_pulse_width_dbg[17]} {dac_pulse_width_dbg[18]} {dac_pulse_width_dbg[19]} {dac_pulse_width_dbg[20]} {dac_pulse_width_dbg[21]} {dac_pulse_width_dbg[22]} {dac_pulse_width_dbg[23]} {dac_pulse_width_dbg[24]} {dac_pulse_width_dbg[25]} {dac_pulse_width_dbg[26]} {dac_pulse_width_dbg[27]} {dac_pulse_width_dbg[28]} {dac_pulse_width_dbg[29]} {dac_pulse_width_dbg[30]} {dac_pulse_width_dbg[31]}]]
|
||||
connect_debug_port u_ila_2/probe4 [get_nets [list dac_rst_dbg]]
|
||||
connect_debug_port u_ila_2/probe5 [get_nets [list dac_start_dbg]]
|
||||
|
||||
|
||||
connect_debug_port u_ila_1/probe7 [get_nets [list p2_wrt_OBUF]]
|
||||
|
||||
create_debug_core u_ila_0 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
|
||||
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/clk]
|
||||
connect_debug_port u_ila_0/clk [get_nets [list rgmii_rxc_IBUF_BUFG]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
||||
set_property port_width 3 [get_debug_ports u_ila_0/probe0]
|
||||
connect_debug_port u_ila_0/probe0 [get_nets [list {udp_ctrl_inst/eth_state[0]} {udp_ctrl_inst/eth_state[1]} {udp_ctrl_inst/eth_state[2]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
||||
set_property port_width 96 [get_debug_ports u_ila_0/probe1]
|
||||
connect_debug_port u_ila_0/probe1 [get_nets [list {udp_ctrl_inst/cfg_bus_eth[0]} {udp_ctrl_inst/cfg_bus_eth[1]} {udp_ctrl_inst/cfg_bus_eth[2]} {udp_ctrl_inst/cfg_bus_eth[3]} {udp_ctrl_inst/cfg_bus_eth[4]} {udp_ctrl_inst/cfg_bus_eth[5]} {udp_ctrl_inst/cfg_bus_eth[6]} {udp_ctrl_inst/cfg_bus_eth[7]} {udp_ctrl_inst/cfg_bus_eth[8]} {udp_ctrl_inst/cfg_bus_eth[9]} {udp_ctrl_inst/cfg_bus_eth[10]} {udp_ctrl_inst/cfg_bus_eth[11]} {udp_ctrl_inst/cfg_bus_eth[12]} {udp_ctrl_inst/cfg_bus_eth[13]} {udp_ctrl_inst/cfg_bus_eth[14]} {udp_ctrl_inst/cfg_bus_eth[15]} {udp_ctrl_inst/cfg_bus_eth[16]} {udp_ctrl_inst/cfg_bus_eth[17]} {udp_ctrl_inst/cfg_bus_eth[18]} {udp_ctrl_inst/cfg_bus_eth[19]} {udp_ctrl_inst/cfg_bus_eth[20]} {udp_ctrl_inst/cfg_bus_eth[21]} {udp_ctrl_inst/cfg_bus_eth[22]} {udp_ctrl_inst/cfg_bus_eth[23]} {udp_ctrl_inst/cfg_bus_eth[24]} {udp_ctrl_inst/cfg_bus_eth[25]} {udp_ctrl_inst/cfg_bus_eth[26]} {udp_ctrl_inst/cfg_bus_eth[27]} {udp_ctrl_inst/cfg_bus_eth[28]} {udp_ctrl_inst/cfg_bus_eth[29]} {udp_ctrl_inst/cfg_bus_eth[30]} {udp_ctrl_inst/cfg_bus_eth[31]} {udp_ctrl_inst/cfg_bus_eth[32]} {udp_ctrl_inst/cfg_bus_eth[33]} {udp_ctrl_inst/cfg_bus_eth[34]} {udp_ctrl_inst/cfg_bus_eth[35]} {udp_ctrl_inst/cfg_bus_eth[36]} {udp_ctrl_inst/cfg_bus_eth[37]} {udp_ctrl_inst/cfg_bus_eth[38]} {udp_ctrl_inst/cfg_bus_eth[39]} {udp_ctrl_inst/cfg_bus_eth[40]} {udp_ctrl_inst/cfg_bus_eth[41]} {udp_ctrl_inst/cfg_bus_eth[42]} {udp_ctrl_inst/cfg_bus_eth[43]} {udp_ctrl_inst/cfg_bus_eth[44]} {udp_ctrl_inst/cfg_bus_eth[45]} {udp_ctrl_inst/cfg_bus_eth[46]} {udp_ctrl_inst/cfg_bus_eth[47]} {udp_ctrl_inst/cfg_bus_eth[48]} {udp_ctrl_inst/cfg_bus_eth[49]} {udp_ctrl_inst/cfg_bus_eth[50]} {udp_ctrl_inst/cfg_bus_eth[51]} {udp_ctrl_inst/cfg_bus_eth[52]} {udp_ctrl_inst/cfg_bus_eth[53]} {udp_ctrl_inst/cfg_bus_eth[54]} {udp_ctrl_inst/cfg_bus_eth[55]} {udp_ctrl_inst/cfg_bus_eth[56]} {udp_ctrl_inst/cfg_bus_eth[57]} {udp_ctrl_inst/cfg_bus_eth[58]} {udp_ctrl_inst/cfg_bus_eth[59]} {udp_ctrl_inst/cfg_bus_eth[60]} {udp_ctrl_inst/cfg_bus_eth[61]} {udp_ctrl_inst/cfg_bus_eth[62]} {udp_ctrl_inst/cfg_bus_eth[63]} {udp_ctrl_inst/cfg_bus_eth[64]} {udp_ctrl_inst/cfg_bus_eth[65]} {udp_ctrl_inst/cfg_bus_eth[66]} {udp_ctrl_inst/cfg_bus_eth[67]} {udp_ctrl_inst/cfg_bus_eth[68]} {udp_ctrl_inst/cfg_bus_eth[69]} {udp_ctrl_inst/cfg_bus_eth[70]} {udp_ctrl_inst/cfg_bus_eth[71]} {udp_ctrl_inst/cfg_bus_eth[72]} {udp_ctrl_inst/cfg_bus_eth[73]} {udp_ctrl_inst/cfg_bus_eth[74]} {udp_ctrl_inst/cfg_bus_eth[75]} {udp_ctrl_inst/cfg_bus_eth[76]} {udp_ctrl_inst/cfg_bus_eth[77]} {udp_ctrl_inst/cfg_bus_eth[78]} {udp_ctrl_inst/cfg_bus_eth[79]} {udp_ctrl_inst/cfg_bus_eth[80]} {udp_ctrl_inst/cfg_bus_eth[81]} {udp_ctrl_inst/cfg_bus_eth[82]} {udp_ctrl_inst/cfg_bus_eth[83]} {udp_ctrl_inst/cfg_bus_eth[84]} {udp_ctrl_inst/cfg_bus_eth[85]} {udp_ctrl_inst/cfg_bus_eth[86]} {udp_ctrl_inst/cfg_bus_eth[87]} {udp_ctrl_inst/cfg_bus_eth[88]} {udp_ctrl_inst/cfg_bus_eth[89]} {udp_ctrl_inst/cfg_bus_eth[90]} {udp_ctrl_inst/cfg_bus_eth[91]} {udp_ctrl_inst/cfg_bus_eth[92]} {udp_ctrl_inst/cfg_bus_eth[93]} {udp_ctrl_inst/cfg_bus_eth[94]} {udp_ctrl_inst/cfg_bus_eth[95]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe2]
|
||||
connect_debug_port u_ila_0/probe2 [get_nets [list {m_axis_rx_tdata[0]} {m_axis_rx_tdata[1]} {m_axis_rx_tdata[2]} {m_axis_rx_tdata[3]} {m_axis_rx_tdata[4]} {m_axis_rx_tdata[5]} {m_axis_rx_tdata[6]} {m_axis_rx_tdata[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe3]
|
||||
connect_debug_port u_ila_0/probe3 [get_nets [list udp_ctrl_inst/axis_hs]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list udp_ctrl_inst/busy_flag_eth]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list m_axis_rx_tlast]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
|
||||
connect_debug_port u_ila_0/probe6 [get_nets [list m_axis_rx_tready]]
|
||||
create_debug_core u_ila_1 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1]
|
||||
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/clk]
|
||||
connect_debug_port u_ila_1/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out1]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
|
||||
set_property port_width 14 [get_debug_ports u_ila_1/probe0]
|
||||
connect_debug_port u_ila_1/probe0 [get_nets [list {p2_data_OBUF[0]} {p2_data_OBUF[1]} {p2_data_OBUF[2]} {p2_data_OBUF[3]} {p2_data_OBUF[4]} {p2_data_OBUF[5]} {p2_data_OBUF[6]} {p2_data_OBUF[7]} {p2_data_OBUF[8]} {p2_data_OBUF[9]} {p2_data_OBUF[10]} {p2_data_OBUF[11]} {p2_data_OBUF[12]} {p2_data_OBUF[13]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe1]
|
||||
connect_debug_port u_ila_1/probe1 [get_nets [list {dac_pulse_num[0]} {dac_pulse_num[1]} {dac_pulse_num[2]} {dac_pulse_num[3]} {dac_pulse_num[4]} {dac_pulse_num[5]} {dac_pulse_num[6]} {dac_pulse_num[7]} {dac_pulse_num[8]} {dac_pulse_num[9]} {dac_pulse_num[10]} {dac_pulse_num[11]} {dac_pulse_num[12]} {dac_pulse_num[13]} {dac_pulse_num[14]} {dac_pulse_num[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2]
|
||||
set_property port_width 14 [get_debug_ports u_ila_1/probe2]
|
||||
connect_debug_port u_ila_1/probe2 [get_nets [list {dac_pulse_height[0]} {dac_pulse_height[1]} {dac_pulse_height[2]} {dac_pulse_height[3]} {dac_pulse_height[4]} {dac_pulse_height[5]} {dac_pulse_height[6]} {dac_pulse_height[7]} {dac_pulse_height[8]} {dac_pulse_height[9]} {dac_pulse_height[10]} {dac_pulse_height[11]} {dac_pulse_height[12]} {dac_pulse_height[13]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3]
|
||||
set_property port_width 32 [get_debug_ports u_ila_1/probe3]
|
||||
connect_debug_port u_ila_1/probe3 [get_nets [list {dac_pulse_period[0]} {dac_pulse_period[1]} {dac_pulse_period[2]} {dac_pulse_period[3]} {dac_pulse_period[4]} {dac_pulse_period[5]} {dac_pulse_period[6]} {dac_pulse_period[7]} {dac_pulse_period[8]} {dac_pulse_period[9]} {dac_pulse_period[10]} {dac_pulse_period[11]} {dac_pulse_period[12]} {dac_pulse_period[13]} {dac_pulse_period[14]} {dac_pulse_period[15]} {dac_pulse_period[16]} {dac_pulse_period[17]} {dac_pulse_period[18]} {dac_pulse_period[19]} {dac_pulse_period[20]} {dac_pulse_period[21]} {dac_pulse_period[22]} {dac_pulse_period[23]} {dac_pulse_period[24]} {dac_pulse_period[25]} {dac_pulse_period[26]} {dac_pulse_period[27]} {dac_pulse_period[28]} {dac_pulse_period[29]} {dac_pulse_period[30]} {dac_pulse_period[31]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4]
|
||||
set_property port_width 32 [get_debug_ports u_ila_1/probe4]
|
||||
connect_debug_port u_ila_1/probe4 [get_nets [list {dac_pulse_width[0]} {dac_pulse_width[1]} {dac_pulse_width[2]} {dac_pulse_width[3]} {dac_pulse_width[4]} {dac_pulse_width[5]} {dac_pulse_width[6]} {dac_pulse_width[7]} {dac_pulse_width[8]} {dac_pulse_width[9]} {dac_pulse_width[10]} {dac_pulse_width[11]} {dac_pulse_width[12]} {dac_pulse_width[13]} {dac_pulse_width[14]} {dac_pulse_width[15]} {dac_pulse_width[16]} {dac_pulse_width[17]} {dac_pulse_width[18]} {dac_pulse_width[19]} {dac_pulse_width[20]} {dac_pulse_width[21]} {dac_pulse_width[22]} {dac_pulse_width[23]} {dac_pulse_width[24]} {dac_pulse_width[25]} {dac_pulse_width[26]} {dac_pulse_width[27]} {dac_pulse_width[28]} {dac_pulse_width[29]} {dac_pulse_width[30]} {dac_pulse_width[31]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe5]
|
||||
connect_debug_port u_ila_1/probe5 [get_nets [list dac_rst]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe6]
|
||||
connect_debug_port u_ila_1/probe6 [get_nets [list dac_start]]
|
||||
create_debug_core u_ila_2 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2]
|
||||
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_2]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_2]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_2]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2]
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/clk]
|
||||
connect_debug_port u_ila_2/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out2]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe0]
|
||||
set_property port_width 8 [get_debug_ports u_ila_2/probe0]
|
||||
connect_debug_port u_ila_2/probe0 [get_nets [list {finish_cnt[0]} {finish_cnt[1]} {finish_cnt[2]} {finish_cnt[3]} {finish_cnt[4]} {finish_cnt[5]} {finish_cnt[6]} {finish_cnt[7]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe1]
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/probe1]
|
||||
connect_debug_port u_ila_2/probe1 [get_nets [list finish_dbg]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe2]
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/probe2]
|
||||
connect_debug_port u_ila_2/probe2 [get_nets [list finish_pending]]
|
||||
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
|
||||
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
|
||||
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
|
||||
connect_debug_port dbg_hub/clk [get_nets adc_clk]
|
||||
@ -1,345 +0,0 @@
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module eth_generator_top #(
|
||||
parameter int unsigned DAC_DATA_WIDTH = 14
|
||||
)(
|
||||
input sys_clk_p,
|
||||
input sys_clk_n,
|
||||
input rst_n,
|
||||
|
||||
output [3:0] led,
|
||||
|
||||
output e_reset,
|
||||
output e_mdc,
|
||||
inout e_mdio,
|
||||
|
||||
output [3:0] rgmii_txd,
|
||||
output rgmii_txctl,
|
||||
output rgmii_txc,
|
||||
input [3:0] rgmii_rxd,
|
||||
input rgmii_rxctl,
|
||||
input rgmii_rxc,
|
||||
|
||||
// DAC
|
||||
output p2_clk,
|
||||
output p2_wrt,
|
||||
(* MARK_DEBUG="true" *) output [13:0] p2_data
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Internal GMII-side signals
|
||||
// -------------------------------------------------------------------------
|
||||
wire [7:0] gmii_txd;
|
||||
wire gmii_tx_en;
|
||||
wire gmii_tx_er;
|
||||
wire gmii_tx_clk;
|
||||
wire gmii_crs;
|
||||
wire gmii_col;
|
||||
wire [7:0] gmii_rxd_i;
|
||||
wire gmii_rx_dv;
|
||||
wire gmii_rx_er;
|
||||
wire gmii_rx_clk;
|
||||
|
||||
wire [31:0] pack_total_len;
|
||||
|
||||
wire e_rx_dv;
|
||||
wire [7:0] e_rxd;
|
||||
wire e_tx_en;
|
||||
wire [7:0] e_txd;
|
||||
wire e_rst_n;
|
||||
wire sys_clk;
|
||||
|
||||
wire duplex_mode;
|
||||
|
||||
|
||||
assign duplex_mode = 1'b1;
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// System clock buffer (200 MHz differential input)
|
||||
// -------------------------------------------------------------------------
|
||||
IBUFDS sys_clk_ibufgds (
|
||||
.O (sys_clk),
|
||||
.I (sys_clk_p),
|
||||
.IB (sys_clk_n)
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// IDELAYCTRL
|
||||
// -------------------------------------------------------------------------
|
||||
(* IODELAY_GROUP = "rgmii_idelay_group" *)
|
||||
IDELAYCTRL IDELAYCTRL_inst (
|
||||
.RDY (),
|
||||
.REFCLK (sys_clk),
|
||||
.RST (1'b0)
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Generated clocks for controller
|
||||
// Need to create this IP in Vivado:
|
||||
// input : 200 MHz
|
||||
// output0: 130 MHz
|
||||
// output1: 65 MHz
|
||||
// -------------------------------------------------------------------------
|
||||
wire dac_clk;
|
||||
wire adc_clk;
|
||||
wire clk_wiz_locked;
|
||||
|
||||
clk_wiz_ctrl_inst clk_wiz_ctrl_inst (
|
||||
.clk_in1 (sys_clk),
|
||||
.reset (~rst_n),
|
||||
.clk_out1 (dac_clk), // 130 MHz
|
||||
.clk_out2 (adc_clk), // 65 MHz
|
||||
.locked (clk_wiz_locked)
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// GMII <-> RGMII conversion
|
||||
// -------------------------------------------------------------------------
|
||||
util_gmii_to_rgmii util_gmii_to_rgmii_m0 (
|
||||
.reset (1'b0),
|
||||
.rgmii_td (rgmii_txd),
|
||||
.rgmii_tx_ctl (rgmii_txctl),
|
||||
.rgmii_txc (rgmii_txc),
|
||||
.rgmii_rd (rgmii_rxd),
|
||||
.rgmii_rx_ctl (rgmii_rxctl),
|
||||
.gmii_rx_clk (gmii_rx_clk),
|
||||
.gmii_txd (e_txd),
|
||||
.gmii_tx_en (e_tx_en),
|
||||
.gmii_tx_er (1'b0),
|
||||
.gmii_tx_clk (gmii_tx_clk),
|
||||
.gmii_crs (gmii_crs),
|
||||
.gmii_col (gmii_col),
|
||||
.gmii_rxd (gmii_rxd_i),
|
||||
.rgmii_rxc (rgmii_rxc),
|
||||
.gmii_rx_dv (gmii_rx_dv),
|
||||
.gmii_rx_er (gmii_rx_er),
|
||||
.speed_selection (2'b10),
|
||||
.duplex_mode (duplex_mode)
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// GMII arbitration / adaptation
|
||||
// -------------------------------------------------------------------------
|
||||
gmii_arbi arbi_inst (
|
||||
.clk (gmii_tx_clk),
|
||||
.rst_n (rst_n),
|
||||
.speed (2'b10),
|
||||
.link (1'b1),
|
||||
.pack_total_len (pack_total_len),
|
||||
.e_rst_n (e_rst_n),
|
||||
.gmii_rx_dv (gmii_rx_dv),
|
||||
.gmii_rxd (gmii_rxd_i),
|
||||
.gmii_tx_en (gmii_tx_en),
|
||||
.gmii_txd (gmii_txd),
|
||||
.e_rx_dv (e_rx_dv),
|
||||
.e_rxd (e_rxd),
|
||||
.e_tx_en (e_tx_en),
|
||||
.e_txd (e_txd)
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// axis_mac interface
|
||||
// RX stream from Ethernet goes into controller
|
||||
// TX stream is unused for now
|
||||
// -------------------------------------------------------------------------
|
||||
wire req_ready;
|
||||
|
||||
reg send_req;
|
||||
reg [15:0] data_length;
|
||||
|
||||
reg [7:0] s_axis_tx_tdata;
|
||||
reg s_axis_tx_tvalid;
|
||||
wire s_axis_tx_tready;
|
||||
reg s_axis_tx_tlast;
|
||||
|
||||
(* MARK_DEBUG="true" *) wire [7:0] m_axis_rx_tdata;
|
||||
(* MARK_DEBUG="true" *) wire m_axis_rx_tvalid;
|
||||
(* MARK_DEBUG="true" *) wire m_axis_rx_tlast;
|
||||
(* MARK_DEBUG="true" *) wire m_axis_rx_tready;
|
||||
|
||||
// Always ready to accept RX payload bytes
|
||||
assign m_axis_rx_tready = 1'b1;
|
||||
|
||||
// TX disabled
|
||||
always @(*) begin
|
||||
send_req = 1'b0;
|
||||
data_length = 16'd0;
|
||||
s_axis_tx_tdata = 8'd0;
|
||||
s_axis_tx_tvalid= 1'b0;
|
||||
s_axis_tx_tlast = 1'b0;
|
||||
end
|
||||
|
||||
axis_mac axis_mac0 (
|
||||
.gmii_tx_clk (gmii_tx_clk),
|
||||
.gmii_rx_clk (gmii_rx_clk),
|
||||
.rst_n (e_rst_n),
|
||||
|
||||
.gmii_rx_dv (e_rx_dv),
|
||||
.gmii_rxd (e_rxd),
|
||||
.gmii_tx_en (gmii_tx_en),
|
||||
.gmii_txd (gmii_txd),
|
||||
|
||||
.send_req (send_req),
|
||||
.data_length (data_length),
|
||||
.req_ready (req_ready),
|
||||
|
||||
.s_axis_tx_tdata (s_axis_tx_tdata),
|
||||
.s_axis_tx_tvalid (s_axis_tx_tvalid),
|
||||
.s_axis_tx_tready (s_axis_tx_tready),
|
||||
.s_axis_tx_tlast (s_axis_tx_tlast),
|
||||
|
||||
.m_axis_rx_tdata (m_axis_rx_tdata),
|
||||
.m_axis_rx_tvalid (m_axis_rx_tvalid),
|
||||
.m_axis_rx_tready (m_axis_rx_tready),
|
||||
.m_axis_rx_tlast (m_axis_rx_tlast)
|
||||
);
|
||||
|
||||
// PHY reset helper from your original example
|
||||
reset reset_m0 (
|
||||
.clk (sys_clk),
|
||||
.key1 (rst_n),
|
||||
.rst_n (e_reset)
|
||||
);
|
||||
|
||||
// MDIO lines are not driven here yet
|
||||
assign e_mdc = 1'b0;
|
||||
assign e_mdio = 1'bz;
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Controller reset
|
||||
// Use both external reset and clk_wiz lock
|
||||
// -------------------------------------------------------------------------
|
||||
wire ctrl_rst_n = rst_n & clk_wiz_locked;
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Debug finish generator (still used here, since generator doesn't have finish signal)
|
||||
//
|
||||
// After each adc_start pulse generates one finish pulse after some delay.
|
||||
// This is just for first bring-up so the controller can leave busy state
|
||||
// If you don't want this, replace with:
|
||||
// wire finish_dbg = 1'b0;
|
||||
// -------------------------------------------------------------------------
|
||||
(* MARK_DEBUG="true" *) logic finish_dbg;
|
||||
(* MARK_DEBUG="true" *) logic [7:0] finish_cnt;
|
||||
(* MARK_DEBUG="true" *) logic finish_pending;
|
||||
|
||||
// Controller outputs to debug
|
||||
(* MARK_DEBUG="true" *) wire [31:0] dac_pulse_width;
|
||||
(* MARK_DEBUG="true" *) wire [31:0] dac_pulse_period;
|
||||
(* MARK_DEBUG="true" *) wire [DAC_DATA_WIDTH-1:0] dac_pulse_height;
|
||||
(* MARK_DEBUG="true" *) wire [15:0] dac_pulse_num;
|
||||
|
||||
(* MARK_DEBUG="true" *) wire [31:0] adc_pulse_period_dbg;
|
||||
(* MARK_DEBUG="true" *) wire [15:0] adc_pulse_num_dbg;
|
||||
|
||||
(* MARK_DEBUG="true" *) wire dac_start;
|
||||
(* MARK_DEBUG="true" *) wire adc_start_dbg;
|
||||
(* MARK_DEBUG="true" *) wire dac_rst;
|
||||
(* MARK_DEBUG="true" *) wire adc_rst_dbg;
|
||||
|
||||
always_ff @(posedge adc_clk or negedge ctrl_rst_n) begin
|
||||
if (!ctrl_rst_n) begin
|
||||
finish_dbg <= 1'b0;
|
||||
finish_cnt <= 8'd0;
|
||||
finish_pending <= 1'b0;
|
||||
end else begin
|
||||
finish_dbg <= 1'b0;
|
||||
|
||||
if (adc_start_dbg) begin
|
||||
finish_pending <= 1'b1;
|
||||
finish_cnt <= 8'd80;
|
||||
end else if (finish_pending) begin
|
||||
if (finish_cnt == 8'd0) begin
|
||||
finish_dbg <= 1'b1;
|
||||
finish_pending <= 1'b0;
|
||||
end else begin
|
||||
finish_cnt <= finish_cnt - 8'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Controller
|
||||
// ETH domain = gmii_rx_clk, because RX AXI master comes from axis_mac RX side
|
||||
// -------------------------------------------------------------------------
|
||||
control #(
|
||||
.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
|
||||
) udp_ctrl_inst (
|
||||
.eth_clk_in (gmii_rx_clk),
|
||||
.dac_clk_in (dac_clk),
|
||||
.adc_clk_in (adc_clk),
|
||||
.rst_n (ctrl_rst_n),
|
||||
|
||||
.s_axis_tdata (m_axis_rx_tdata),
|
||||
.s_axis_tvalid (m_axis_rx_tvalid),
|
||||
.s_axis_tready (), // controller internally always ready in current version
|
||||
.s_axis_tlast (m_axis_rx_tlast),
|
||||
|
||||
.finish (finish_dbg),
|
||||
|
||||
.dac_pulse_width (dac_pulse_width),
|
||||
.dac_pulse_period (dac_pulse_period),
|
||||
.dac_pulse_height (dac_pulse_height),
|
||||
.dac_pulse_num (dac_pulse_num),
|
||||
|
||||
.adc_pulse_period (adc_pulse_period_dbg),
|
||||
.adc_pulse_num (adc_pulse_num_dbg),
|
||||
|
||||
.dac_start (dac_start),
|
||||
.adc_start (adc_start_dbg),
|
||||
|
||||
.dac_rst (dac_rst),
|
||||
.adc_rst (adc_rst_dbg)
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// DAC
|
||||
// -------------------------------------------------------------------------
|
||||
generator #(
|
||||
.DATA_WIDTH(DAC_DATA_WIDTH)
|
||||
) generator_inst (
|
||||
.clk_in(dac_clk),
|
||||
.rst(dac_rst),
|
||||
.start(dac_start),
|
||||
.pulse_width(dac_pulse_width),
|
||||
.pulse_period(dac_pulse_period),
|
||||
.pulse_height(dac_pulse_height),
|
||||
.pulse_num(dac_pulse_num),
|
||||
.pulse(p2_wrt ),
|
||||
.pulse_height_out(p2_data)
|
||||
);
|
||||
|
||||
// dac clk mgt
|
||||
wire p2_clk_oddr;
|
||||
|
||||
ODDR #(
|
||||
.DDR_CLK_EDGE("SAME_EDGE"),
|
||||
.INIT(1'b0),
|
||||
.SRTYPE("SYNC")
|
||||
) ODDR_p2_clk (
|
||||
.Q (p2_clk_oddr),
|
||||
.C (dac_clk),
|
||||
.CE(1'b1),
|
||||
.D1(1'b1),
|
||||
.D2(1'b0),
|
||||
.R (1'b0),
|
||||
.S (1'b0)
|
||||
);
|
||||
|
||||
OBUF OBUF_p2_clk (
|
||||
.I(p2_clk_oddr),
|
||||
.O(p2_clk)
|
||||
);
|
||||
|
||||
//assign p2_wrt = p2_clk;
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Simple LED status
|
||||
// -------------------------------------------------------------------------
|
||||
assign led[0] = clk_wiz_locked;
|
||||
assign led[1] = m_axis_rx_tvalid;
|
||||
assign led[2] = dac_start;
|
||||
assign led[3] = adc_rst_dbg;
|
||||
|
||||
endmodule
|
||||
@ -7,8 +7,8 @@
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xc7a35tfgg484-1
|
||||
FPGA_TOP = eth_generator_top
|
||||
FPGA_PART = xc7a100tfgg484-2
|
||||
FPGA_TOP = reflectometer_top
|
||||
FPGA_ARCH = artix7
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
@ -16,13 +16,13 @@ RTL_DIR = ../../rtl
|
||||
|
||||
include ../../scripts/vivado.mk
|
||||
|
||||
SYN_FILES += eth_generator.sv
|
||||
SYN_FILES += reflectometer.sv
|
||||
SYN_FILES += $(sort $(shell find ../../rtl -type f \( -name '*.v' -o -name '*.sv' \)))
|
||||
|
||||
XCI_FILES = $(sort $(shell find ../../rtl/ethernet-udp/src -type f -name '*.xci'))
|
||||
XCI_FILES += $(sort $(shell find ip/ -type f -name '*.xci'))
|
||||
|
||||
XDC_FILES += ../../constraints/ax7a035b.xdc
|
||||
XDC_FILES += ../../constraints/ax7102.xdc
|
||||
XDC_FILES += debug.xdc
|
||||
|
||||
|
||||
145
designs/reflectometer_base/README.md
Normal file
145
designs/reflectometer_base/README.md
Normal file
@ -0,0 +1,145 @@
|
||||
# Рефлектометр
|
||||
|
||||
Модуль представляет собой законченную встраиваемую систему рефлектометра, объединяющую:
|
||||
|
||||
- контроллер управления
|
||||
- генератор импульсов (DAC path)
|
||||
- сэмплер данных (ADC path)
|
||||
- аккумулятор и обработчик данных
|
||||
|
||||
Система предназначена для формирования импульсов, синхронного сбора отраженного сигнала, накопления результатов и передачи обработанных данных во внешнюю систему.
|
||||
|
||||
Данный модуль является полноценным интегрируемым блоком, который может использоваться как самостоятельная аппаратная подсистема внутри более крупного проекта.
|
||||
|
||||
---
|
||||
|
||||
## Назначение системы
|
||||
|
||||
Основная задача системы:
|
||||
|
||||
1. Получить параметры измерения через AXI Stream
|
||||
2. Сформировать последовательность импульсов на DAC
|
||||
3. Выполнить синходную выборку данных с ADC
|
||||
4. Накопить и обработать результаты
|
||||
5. Передать итоговые данные обратно через AXI Stream
|
||||
|
||||
Таким образом реализуется полный цикл измерения без необходимости внешнего управления отдельными блоками.
|
||||
|
||||
---
|
||||
|
||||
## Состав системы
|
||||
|
||||
### Controller
|
||||
|
||||
Принимает входные команды по AXI Stream (Ethernet RX), декодирует параметры измерения и управляет всеми внутренними модулями системы.
|
||||
|
||||
Формирует:
|
||||
|
||||
- запуск генератора (`dac_start`)
|
||||
- запуск аккумулятора (`adc_start`)
|
||||
- параметры импульсов DAC
|
||||
- параметры выборки ADC
|
||||
- локальные reset-сигналы
|
||||
|
||||
---
|
||||
|
||||
### Generator
|
||||
|
||||
Формирует последовательность импульсов на DAC с заданными:
|
||||
|
||||
- амплитудой
|
||||
- длительностью
|
||||
- периодом
|
||||
- количеством повторений
|
||||
|
||||
Для каждого импульса инициирует запуск выборки в сэмплере.
|
||||
|
||||
---
|
||||
|
||||
### Sampler
|
||||
|
||||
Выполняет синхронный сбор данных с ADC по запросу генератора.
|
||||
|
||||
Поддерживает:
|
||||
|
||||
- фильтрацию `out_of_range`
|
||||
- упаковку данных
|
||||
- преобразование типа кода ( прямой или дополнительный)
|
||||
|
||||
---
|
||||
|
||||
### Accumulator
|
||||
|
||||
Получает поток данных от сэмплера, выполняет накопление, усреднение и оконную обработку, после чего формирует пакеты для передачи результата.
|
||||
|
||||
---
|
||||
|
||||
## Управление системой
|
||||
|
||||
Пользователь взаимодействует только с контроллером через AXI Stream-интерфейс.
|
||||
|
||||
Прямое управление генератором, сэмплером и аккумулятором не требуется.
|
||||
|
||||
---
|
||||
|
||||
## Clock Domain Crossing (CDC)
|
||||
|
||||
Система работает в нескольких тактовых доменах:
|
||||
|
||||
- Ethernet RX (`gmii_rx_clk`)
|
||||
- Ethernet TX (`gmii_tx_clk`)
|
||||
- DAC (`dac_clk`)
|
||||
- ADC (`adc_clk`)
|
||||
|
||||
Для корректной синхронизации между DAC и ADC используются специальные CDC-регистры для сигналов:
|
||||
|
||||
- `sample_req`
|
||||
- `sample_done`
|
||||
|
||||
Это обеспечивает безопасную передачу handshake-сигналов между тактовыми доменами.
|
||||
|
||||
---
|
||||
|
||||
## Список параметров
|
||||
|
||||
### DAC_DATA_WIDTH
|
||||
Ширина выходных данных отправляемых на ЦАП.
|
||||
|
||||
### ZERO_LEVEL
|
||||
Уровень сигнала в состоянии отсутствия импульса (базовый уровень сигнала).
|
||||
|
||||
Типовые значения:
|
||||
|
||||
- `8192` — середина диапазона ЦАП
|
||||
- `0` — нулевой уровень
|
||||
|
||||
### ADC_DATA_WIDTH
|
||||
Ширина входных данных, получаемых с АЦП.
|
||||
|
||||
### PACK_FACTOR
|
||||
Количество отсчетов, собираемых в один выходной пакет.
|
||||
|
||||
### PROCESS_MODE
|
||||
Режим интерпретации входного кода:
|
||||
|
||||
- `0` — прямой код
|
||||
- `1` — дополнительный код
|
||||
|
||||
### ACCUM_WIDTH
|
||||
Размер данных для аккумуляции, должен быть степенью числа 2. По умолчанию - 32
|
||||
|
||||
### N_MAX
|
||||
Максимальное число окон в последовательности. Должно быть степенью числа 2. Влияет на размер используемой памяти.
|
||||
|
||||
### WINDOW_SIZE
|
||||
Размер окна усреднения
|
||||
|
||||
### PACKET_SIZE
|
||||
Размер выходного пакета
|
||||
|
||||
---
|
||||
|
||||
## Сборка
|
||||
```make all``` - собрать все до битстрима
|
||||
|
||||
```make vivado``` - открыть проект в Vivado
|
||||
1
designs/reflectometer_base/debug.xdc
Normal file
1
designs/reflectometer_base/debug.xdc
Normal file
@ -0,0 +1 @@
|
||||
set_clock_groups -name ASYNC_UDP_CTRL -asynchronous -group [get_clocks rgmii_rxc] -group [get_clocks clk_out1_clk_wiz_ctrl_inst] -group [get_clocks clk_out2_clk_wiz_ctrl_inst]
|
||||
320
designs/reflectometer_base/reflectometer.sv
Normal file
320
designs/reflectometer_base/reflectometer.sv
Normal file
@ -0,0 +1,320 @@
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module reflectometer_top #(
|
||||
parameter int unsigned DAC_DATA_WIDTH = 14,
|
||||
parameter int unsigned ADC_DATA_WIDTH = 12,
|
||||
parameter PACK_FACTOR = 1,
|
||||
parameter PROCESS_MODE = 0,
|
||||
parameter ZERO_LEVEL = 8192,
|
||||
parameter ACCUM_WIDTH = 32,
|
||||
parameter N_MAX = 4096,
|
||||
parameter WINDOW_SIZE = 65,
|
||||
parameter PACKET_SIZE = 1024
|
||||
)(
|
||||
input sys_clk,
|
||||
input rst_n,
|
||||
|
||||
output [3:0] led,
|
||||
|
||||
input gmii_rx_clk,
|
||||
input gmii_tx_clk,
|
||||
|
||||
(* MARK_DEBUG="true" *) output logic [7:0] s_axis_tx_tdata,
|
||||
(* MARK_DEBUG="true" *) output logic s_axis_tx_tvalid,
|
||||
(* MARK_DEBUG="true" *) input logic s_axis_tx_tready,
|
||||
(* MARK_DEBUG="true" *) output logic s_axis_tx_tlast,
|
||||
|
||||
(* MARK_DEBUG="true" *) input wire [7:0] m_axis_rx_tdata,
|
||||
(* MARK_DEBUG="true" *) input wire m_axis_rx_tvalid,
|
||||
(* MARK_DEBUG="true" *) input wire m_axis_rx_tlast,
|
||||
(* MARK_DEBUG="true" *) output wire m_axis_rx_tready,
|
||||
|
||||
// axis_mac
|
||||
|
||||
(* MARK_DEBUG="true" *) input logic req_ready,
|
||||
(* MARK_DEBUG="true" *) output logic send_req,
|
||||
|
||||
// DAC
|
||||
|
||||
output wire p2_clk,
|
||||
(* MARK_DEBUG="true" *) output wire [DAC_DATA_WIDTH-1:0] p2_data,
|
||||
(* MARK_DEBUG="true" *) output wire p2_wrt,
|
||||
|
||||
// ADC
|
||||
output ch2_clk,
|
||||
(* MARK_DEBUG="true" *) input [ADC_DATA_WIDTH-1:0] ch2_data,
|
||||
input ch2_otr
|
||||
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// IDELAYCTRL
|
||||
// -------------------------------------------------------------------------
|
||||
(* IODELAY_GROUP = "rgmii_idelay_group" *)
|
||||
IDELAYCTRL IDELAYCTRL_inst (
|
||||
.RDY (),
|
||||
.REFCLK (sys_clk),
|
||||
.RST (1'b0)
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Generated clocks for controller
|
||||
// Need to create this IP in Vivado:
|
||||
// input : 200 MHz
|
||||
// output0: 130 MHz
|
||||
// output1: 65 MHz
|
||||
// -------------------------------------------------------------------------
|
||||
wire dac_clk;
|
||||
wire adc_clk;
|
||||
wire clk_wiz_locked;
|
||||
|
||||
clk_wiz_ctrl_inst clk_wiz_ctrl_inst (
|
||||
.clk_in1 (sys_clk),
|
||||
.reset (~rst_n),
|
||||
.clk_out1 (dac_clk), // 130 MHz
|
||||
.clk_out2 (adc_clk), // 65 MHz
|
||||
.locked (clk_wiz_locked)
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// axis_mac interface
|
||||
// RX stream from Ethernet goes into controller
|
||||
// TX stream is unused for now
|
||||
// -------------------------------------------------------------------------
|
||||
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Controller reset
|
||||
// Use both external reset and clk_wiz lock
|
||||
// -------------------------------------------------------------------------
|
||||
wire ctrl_rst_n = rst_n & clk_wiz_locked;
|
||||
|
||||
|
||||
(* MARK_DEBUG="true" *) logic finish;
|
||||
|
||||
// Controller outputs to debug
|
||||
(* MARK_DEBUG="true" *) wire [31:0] dac_pulse_width;
|
||||
(* MARK_DEBUG="true" *) wire [31:0] dac_pulse_period;
|
||||
(* MARK_DEBUG="true" *) wire [DAC_DATA_WIDTH-1:0] dac_pulse_height;
|
||||
(* MARK_DEBUG="true" *) wire [15:0] dac_pulse_num;
|
||||
|
||||
(* MARK_DEBUG="true" *) wire [31:0] adc_pulse_period;
|
||||
(* MARK_DEBUG="true" *) wire [15:0] adc_pulse_num;
|
||||
|
||||
(* MARK_DEBUG="true" *) wire dac_start;
|
||||
(* MARK_DEBUG="true" *) wire adc_start;
|
||||
(* MARK_DEBUG="true" *) wire dac_rst;
|
||||
(* MARK_DEBUG="true" *) wire adc_rst;
|
||||
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Controller
|
||||
// ETH domain = gmii_rx_clk, because RX AXI master comes from axis_mac RX side
|
||||
// -------------------------------------------------------------------------
|
||||
control #(
|
||||
.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
|
||||
) udp_ctrl_inst (
|
||||
.eth_clk_in (gmii_rx_clk),
|
||||
.dac_clk_in (dac_clk),
|
||||
.adc_clk_in (adc_clk),
|
||||
.rst_n (ctrl_rst_n),
|
||||
|
||||
.s_axis_tdata (m_axis_rx_tdata),
|
||||
.s_axis_tvalid (m_axis_rx_tvalid),
|
||||
.s_axis_tready (m_axis_rx_tready),
|
||||
.s_axis_tlast (m_axis_rx_tlast),
|
||||
|
||||
.finish (finish),
|
||||
|
||||
.dac_pulse_width (dac_pulse_width),
|
||||
.dac_pulse_period (dac_pulse_period),
|
||||
.dac_pulse_height (dac_pulse_height),
|
||||
.dac_pulse_num (dac_pulse_num),
|
||||
|
||||
.adc_pulse_period (adc_pulse_period),
|
||||
.adc_pulse_num (adc_pulse_num),
|
||||
|
||||
.dac_start (dac_start),
|
||||
.adc_start (adc_start),
|
||||
|
||||
.dac_rst (dac_rst),
|
||||
.adc_rst (adc_rst)
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// DAC
|
||||
// -------------------------------------------------------------------------
|
||||
|
||||
(* MARK_DEBUG="true" *) logic sample_req;
|
||||
(* MARK_DEBUG="true" *) logic sample_req_sync1;
|
||||
(* MARK_DEBUG="true" *) logic sample_req_sync2;
|
||||
(* MARK_DEBUG="true" *) logic sample_req_sync3;
|
||||
|
||||
(* MARK_DEBUG="true" *) logic sample_done;
|
||||
(* MARK_DEBUG="true" *) logic sample_done_sync1;
|
||||
(* MARK_DEBUG="true" *) logic sample_done_sync2;
|
||||
(* MARK_DEBUG="true" *) logic sample_done_sync3;
|
||||
|
||||
//------------------------------------------------------------
|
||||
// DAC -> ADC CDC
|
||||
//------------------------------------------------------------
|
||||
always_ff @(posedge adc_clk or posedge adc_rst) begin
|
||||
if (adc_rst) begin
|
||||
sample_req <= 1'b0;
|
||||
sample_req_sync2 <= 1'b0;
|
||||
sample_req_sync3 <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
sample_req_sync2 <= sample_req_sync1;
|
||||
sample_req_sync3 <= sample_req_sync2;
|
||||
sample_req <= sample_req_sync3;
|
||||
end
|
||||
end
|
||||
|
||||
//------------------------------------------------------------
|
||||
// ADC -> DAC CDC
|
||||
//------------------------------------------------------------
|
||||
always_ff @(posedge dac_clk or posedge dac_rst) begin
|
||||
if (dac_rst) begin
|
||||
sample_done <= 1'b0;
|
||||
sample_done_sync2 <= 1'b0;
|
||||
sample_done_sync3 <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
sample_done_sync2 <= sample_done_sync1;
|
||||
sample_done_sync3 <= sample_done_sync2;
|
||||
sample_done <= sample_done_sync3;
|
||||
end
|
||||
end
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Generator
|
||||
//------------------------------------------------------------
|
||||
|
||||
generator #(
|
||||
.DATA_WIDTH(DAC_DATA_WIDTH),
|
||||
.ZERO_LEVEL(ZERO_LEVEL)
|
||||
) generator_inst (
|
||||
.clk_in(dac_clk),
|
||||
.rst(dac_rst),
|
||||
.start(dac_start),
|
||||
.pulse_width(dac_pulse_width),
|
||||
.pulse_period(dac_pulse_period),
|
||||
.pulse_height(dac_pulse_height),
|
||||
.pulse_num(dac_pulse_num),
|
||||
.pulse(p2_wrt),
|
||||
.pulse_height_out(p2_data),
|
||||
.sample_done(sample_done),
|
||||
.sample_req(sample_req_sync1)
|
||||
);
|
||||
|
||||
wire ch2_clk_oddr;
|
||||
|
||||
ODDR #(
|
||||
.DDR_CLK_EDGE("SAME_EDGE"),
|
||||
.INIT(1'b0),
|
||||
.SRTYPE("SYNC")
|
||||
) ODDR_ch2_clk (
|
||||
.Q (ch2_clk_oddr),
|
||||
.C (adc_clk),
|
||||
.CE(1'b1),
|
||||
.D1(1'b1),
|
||||
.D2(1'b0),
|
||||
.R (1'b0),
|
||||
.S (1'b0)
|
||||
);
|
||||
|
||||
OBUF OBUF_ch2_clk (
|
||||
.I(ch2_clk_oddr),
|
||||
.O(ch2_clk)
|
||||
);
|
||||
|
||||
wire p2_clk_oddr;
|
||||
|
||||
ODDR #(
|
||||
.DDR_CLK_EDGE("SAME_EDGE"),
|
||||
.INIT(1'b0),
|
||||
.SRTYPE("SYNC")
|
||||
) ODDR_p2_clk (
|
||||
.Q (p2_clk_oddr),
|
||||
.C (dac_clk),
|
||||
.CE(1'b1),
|
||||
.D1(1'b1),
|
||||
.D2(1'b0),
|
||||
.R (1'b0),
|
||||
.S (1'b0)
|
||||
);
|
||||
|
||||
OBUF OBUF_p2_clk (
|
||||
.I(p2_clk_oddr),
|
||||
.O(p2_clk)
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// ADC
|
||||
// -------------------------------------------------------------------------
|
||||
|
||||
(* MARK_DEBUG="true" *) logic [ADC_DATA_WIDTH*PACK_FACTOR-1:0] accum_m_axis_tdata;
|
||||
(* MARK_DEBUG="true" *) logic acum_m_axis_tvalid;
|
||||
|
||||
sampler
|
||||
#(
|
||||
.DATA_WIDTH(ADC_DATA_WIDTH),
|
||||
.PACK_FACTOR(PACK_FACTOR),
|
||||
.PROCESS_MODE(PROCESS_MODE)
|
||||
)
|
||||
sampler_dut
|
||||
(
|
||||
.clk_in(adc_clk),
|
||||
.rst(adc_rst),
|
||||
.data_in(ch2_data),
|
||||
.out_of_range(ch2_otr),
|
||||
.m_axis_tdata(accum_m_axis_tdata),
|
||||
.m_axis_tvalid(acum_m_axis_tvalid),
|
||||
.smp_num(adc_pulse_period),
|
||||
.sample_req(sample_req),
|
||||
.sample_done(sample_done_sync1)
|
||||
);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Accumulator
|
||||
// -------------------------------------------------------------------------
|
||||
|
||||
accumulator_top
|
||||
#(
|
||||
.DATA_WIDTH(ADC_DATA_WIDTH),
|
||||
.ACCUM_WIDTH(ACCUM_WIDTH),
|
||||
.N_MAX(N_MAX),
|
||||
.WINDOW_SIZE(WINDOW_SIZE),
|
||||
.PACKET_SIZE(PACKET_SIZE)
|
||||
)
|
||||
accumulator_top_dut
|
||||
(
|
||||
.clk_in(adc_clk),
|
||||
.rst(adc_rst),
|
||||
.s_axis_tdata(accum_m_axis_tdata),
|
||||
.s_axis_tvalid(acum_m_axis_tvalid),
|
||||
.start(adc_start),
|
||||
.smp_num(adc_pulse_period),
|
||||
.seq_num(adc_pulse_num),
|
||||
|
||||
.eth_clk_in(gmii_tx_clk),
|
||||
.req_ready(req_ready),
|
||||
.send_req(send_req),
|
||||
.m_axis_tdata(s_axis_tx_tdata),
|
||||
.m_axis_tvalid(s_axis_tx_tvalid),
|
||||
.m_axis_tready(s_axis_tx_tready),
|
||||
.m_axis_tlast(s_axis_tx_tlast),
|
||||
|
||||
.finish(finish)
|
||||
);
|
||||
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Simple LED status
|
||||
// -------------------------------------------------------------------------
|
||||
assign led[0] = clk_wiz_locked;
|
||||
assign led[1] = m_axis_rx_tvalid;
|
||||
assign led[2] = dac_start;
|
||||
|
||||
endmodule
|
||||
@ -7,8 +7,8 @@
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xc7a35tfgg484-1
|
||||
FPGA_TOP = eth_ctrl_debug_top
|
||||
FPGA_PART = xc7a100tfgg484-2
|
||||
FPGA_TOP = prototype_top
|
||||
FPGA_ARCH = artix7
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
@ -16,13 +16,14 @@ RTL_DIR = ../../rtl
|
||||
|
||||
include ../../scripts/vivado.mk
|
||||
|
||||
SYN_FILES += eth_ctrl_debug.sv
|
||||
SYN_FILES += prototype.sv
|
||||
SYN_FILES += ../reflectometer_base/reflectometer.sv
|
||||
SYN_FILES += $(sort $(shell find ../../rtl -type f \( -name '*.v' -o -name '*.sv' \)))
|
||||
|
||||
XCI_FILES = $(sort $(shell find ../../rtl/ethernet-udp/src -type f -name '*.xci'))
|
||||
XCI_FILES += $(sort $(shell find ip/ -type f -name '*.xci'))
|
||||
|
||||
XDC_FILES += ../../constraints/ax7a035b.xdc
|
||||
XDC_FILES += ../../constraints/ax7102.xdc
|
||||
XDC_FILES += debug.xdc
|
||||
|
||||
|
||||
13
designs/reflectometer_prototype/README.md
Normal file
13
designs/reflectometer_prototype/README.md
Normal file
@ -0,0 +1,13 @@
|
||||
# Тестовый проект рефлектометра
|
||||
Проект состоит из AXIS Ethernet и основной части рефлектометра - генератора, сэмплера, контроллера и синхронизирующей логики. Разработан для AX7102, АЦП AN9238, ЦАП AD9767. Плата подключается по ethernet к компьютеру, IP должен быть 192.168.0.3 у компьютера, в ПЛИС установлен IP 192.168.0.2, после подключения должен пройти ARP и после этого можно начнить коммуникацию через консольку.
|
||||
## Сборка
|
||||
```make all``` - собрать все до битстрима
|
||||
|
||||
```make vivado``` - открыть проект в Vivado
|
||||
|
||||
## Управление
|
||||
Используйте software/console.py. Примеры:
|
||||
|
||||
```python3 console.py --pulse_width 3500 --pulse_period 20000 --pulse_height 15000 --pulse_num 550 --dac-bits 14```
|
||||
|
||||
```python3 console.py --pulse_width 15000 --pulse_period 20000 --pulse_height 1500 --pulse_num 550 --dac-bits 14```
|
||||
238
designs/reflectometer_prototype/debug.xdc
Normal file
238
designs/reflectometer_prototype/debug.xdc
Normal file
@ -0,0 +1,238 @@
|
||||
set_clock_groups -name ASYNC_UDP_CTRL -asynchronous -group [get_clocks rx_clk] -group [get_clocks clk_out1_clk_wiz_ctrl_inst] -group [get_clocks clk_out2_clk_wiz_ctrl_inst]
|
||||
|
||||
|
||||
|
||||
|
||||
connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out2]]
|
||||
connect_debug_port u_ila_0/probe0 [get_nets [list {accumulator_top_dut/output_async_fifo/wr_state[0]} {accumulator_top_dut/output_async_fifo/wr_state[1]} {accumulator_top_dut/output_async_fifo/wr_state[2]}]]
|
||||
connect_debug_port u_ila_0/probe1 [get_nets [list {sampler_dut/smp_num_reg[0]} {sampler_dut/smp_num_reg[1]} {sampler_dut/smp_num_reg[2]} {sampler_dut/smp_num_reg[3]} {sampler_dut/smp_num_reg[4]} {sampler_dut/smp_num_reg[5]} {sampler_dut/smp_num_reg[6]} {sampler_dut/smp_num_reg[7]} {sampler_dut/smp_num_reg[8]} {sampler_dut/smp_num_reg[9]} {sampler_dut/smp_num_reg[10]} {sampler_dut/smp_num_reg[11]} {sampler_dut/smp_num_reg[12]} {sampler_dut/smp_num_reg[13]} {sampler_dut/smp_num_reg[14]} {sampler_dut/smp_num_reg[15]} {sampler_dut/smp_num_reg[16]} {sampler_dut/smp_num_reg[17]} {sampler_dut/smp_num_reg[18]} {sampler_dut/smp_num_reg[19]} {sampler_dut/smp_num_reg[20]} {sampler_dut/smp_num_reg[21]} {sampler_dut/smp_num_reg[22]} {sampler_dut/smp_num_reg[23]} {sampler_dut/smp_num_reg[24]} {sampler_dut/smp_num_reg[25]} {sampler_dut/smp_num_reg[26]} {sampler_dut/smp_num_reg[27]} {sampler_dut/smp_num_reg[28]} {sampler_dut/smp_num_reg[29]} {sampler_dut/smp_num_reg[30]} {sampler_dut/smp_num_reg[31]}]]
|
||||
connect_debug_port u_ila_0/probe2 [get_nets [list {adc_pulse_num[0]} {adc_pulse_num[1]} {adc_pulse_num[2]} {adc_pulse_num[3]} {adc_pulse_num[4]} {adc_pulse_num[5]} {adc_pulse_num[6]} {adc_pulse_num[7]} {adc_pulse_num[8]} {adc_pulse_num[9]} {adc_pulse_num[10]} {adc_pulse_num[11]} {adc_pulse_num[12]} {adc_pulse_num[13]} {adc_pulse_num[14]} {adc_pulse_num[15]}]]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list {accum_m_axis_tdata[0]} {accum_m_axis_tdata[1]} {accum_m_axis_tdata[2]} {accum_m_axis_tdata[3]} {accum_m_axis_tdata[4]} {accum_m_axis_tdata[5]} {accum_m_axis_tdata[6]} {accum_m_axis_tdata[7]} {accum_m_axis_tdata[8]} {accum_m_axis_tdata[9]} {accum_m_axis_tdata[10]} {accum_m_axis_tdata[11]}]]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list {sampler_dut/cnt_smp_num[0]} {sampler_dut/cnt_smp_num[1]} {sampler_dut/cnt_smp_num[2]} {sampler_dut/cnt_smp_num[3]} {sampler_dut/cnt_smp_num[4]} {sampler_dut/cnt_smp_num[5]} {sampler_dut/cnt_smp_num[6]} {sampler_dut/cnt_smp_num[7]} {sampler_dut/cnt_smp_num[8]} {sampler_dut/cnt_smp_num[9]} {sampler_dut/cnt_smp_num[10]} {sampler_dut/cnt_smp_num[11]} {sampler_dut/cnt_smp_num[12]} {sampler_dut/cnt_smp_num[13]} {sampler_dut/cnt_smp_num[14]} {sampler_dut/cnt_smp_num[15]} {sampler_dut/cnt_smp_num[16]} {sampler_dut/cnt_smp_num[17]} {sampler_dut/cnt_smp_num[18]} {sampler_dut/cnt_smp_num[19]} {sampler_dut/cnt_smp_num[20]} {sampler_dut/cnt_smp_num[21]} {sampler_dut/cnt_smp_num[22]} {sampler_dut/cnt_smp_num[23]} {sampler_dut/cnt_smp_num[24]} {sampler_dut/cnt_smp_num[25]} {sampler_dut/cnt_smp_num[26]} {sampler_dut/cnt_smp_num[27]} {sampler_dut/cnt_smp_num[28]} {sampler_dut/cnt_smp_num[29]} {sampler_dut/cnt_smp_num[30]} {sampler_dut/cnt_smp_num[31]}]]
|
||||
connect_debug_port u_ila_0/probe6 [get_nets [list {sampler_dut/data_converted[0]} {sampler_dut/data_converted[1]} {sampler_dut/data_converted[2]} {sampler_dut/data_converted[3]} {sampler_dut/data_converted[4]} {sampler_dut/data_converted[5]} {sampler_dut/data_converted[6]} {sampler_dut/data_converted[7]} {sampler_dut/data_converted[8]} {sampler_dut/data_converted[9]} {sampler_dut/data_converted[10]} {sampler_dut/data_converted[11]}]]
|
||||
connect_debug_port u_ila_0/probe7 [get_nets [list {adc_pulse_period[0]} {adc_pulse_period[1]} {adc_pulse_period[2]} {adc_pulse_period[3]} {adc_pulse_period[4]} {adc_pulse_period[5]} {adc_pulse_period[6]} {adc_pulse_period[7]} {adc_pulse_period[8]} {adc_pulse_period[9]} {adc_pulse_period[10]} {adc_pulse_period[11]} {adc_pulse_period[12]} {adc_pulse_period[13]} {adc_pulse_period[14]} {adc_pulse_period[15]} {adc_pulse_period[16]} {adc_pulse_period[17]} {adc_pulse_period[18]} {adc_pulse_period[19]} {adc_pulse_period[20]} {adc_pulse_period[21]} {adc_pulse_period[22]} {adc_pulse_period[23]} {adc_pulse_period[24]} {adc_pulse_period[25]} {adc_pulse_period[26]} {adc_pulse_period[27]} {adc_pulse_period[28]} {adc_pulse_period[29]} {adc_pulse_period[30]} {adc_pulse_period[31]}]]
|
||||
connect_debug_port u_ila_0/probe8 [get_nets [list {accumulator_top_dut/accum_main/wr_state[0]} {accumulator_top_dut/accum_main/wr_state[1]} {accumulator_top_dut/accum_main/wr_state[2]} {accumulator_top_dut/accum_main/wr_state[3]}]]
|
||||
connect_debug_port u_ila_0/probe9 [get_nets [list {accumulator_top_dut/accum_main/adder_dut/cnt[0]} {accumulator_top_dut/accum_main/adder_dut/cnt[1]} {accumulator_top_dut/accum_main/adder_dut/cnt[2]} {accumulator_top_dut/accum_main/adder_dut/cnt[3]} {accumulator_top_dut/accum_main/adder_dut/cnt[4]} {accumulator_top_dut/accum_main/adder_dut/cnt[5]} {accumulator_top_dut/accum_main/adder_dut/cnt[6]} {accumulator_top_dut/accum_main/adder_dut/cnt[7]} {accumulator_top_dut/accum_main/adder_dut/cnt[8]} {accumulator_top_dut/accum_main/adder_dut/cnt[9]} {accumulator_top_dut/accum_main/adder_dut/cnt[10]} {accumulator_top_dut/accum_main/adder_dut/cnt[11]} {accumulator_top_dut/accum_main/adder_dut/cnt[12]} {accumulator_top_dut/accum_main/adder_dut/cnt[13]} {accumulator_top_dut/accum_main/adder_dut/cnt[14]} {accumulator_top_dut/accum_main/adder_dut/cnt[15]}]]
|
||||
connect_debug_port u_ila_0/probe10 [get_nets [list acum_m_axis_tvalid]]
|
||||
connect_debug_port u_ila_0/probe11 [get_nets [list adc_rst]]
|
||||
connect_debug_port u_ila_0/probe12 [get_nets [list adc_start]]
|
||||
connect_debug_port u_ila_0/probe13 [get_nets [list sampler_dut/enable]]
|
||||
connect_debug_port u_ila_0/probe14 [get_nets [list finish]]
|
||||
connect_debug_port u_ila_0/probe15 [get_nets [list sampler_dut/out_of_range_reg]]
|
||||
connect_debug_port u_ila_0/probe16 [get_nets [list sample_req]]
|
||||
connect_debug_port u_ila_1/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out1]]
|
||||
connect_debug_port u_ila_1/probe0 [get_nets [list {generator_inst/pulse_num_reg[0]} {generator_inst/pulse_num_reg[1]} {generator_inst/pulse_num_reg[2]} {generator_inst/pulse_num_reg[3]} {generator_inst/pulse_num_reg[4]} {generator_inst/pulse_num_reg[5]} {generator_inst/pulse_num_reg[6]} {generator_inst/pulse_num_reg[7]} {generator_inst/pulse_num_reg[8]} {generator_inst/pulse_num_reg[9]} {generator_inst/pulse_num_reg[10]} {generator_inst/pulse_num_reg[11]} {generator_inst/pulse_num_reg[12]} {generator_inst/pulse_num_reg[13]} {generator_inst/pulse_num_reg[14]} {generator_inst/pulse_num_reg[15]}]]
|
||||
connect_debug_port u_ila_1/probe1 [get_nets [list {dac_pulse_num[0]} {dac_pulse_num[1]} {dac_pulse_num[2]} {dac_pulse_num[3]} {dac_pulse_num[4]} {dac_pulse_num[5]} {dac_pulse_num[6]} {dac_pulse_num[7]} {dac_pulse_num[8]} {dac_pulse_num[9]} {dac_pulse_num[10]} {dac_pulse_num[11]} {dac_pulse_num[12]} {dac_pulse_num[13]} {dac_pulse_num[14]} {dac_pulse_num[15]}]]
|
||||
connect_debug_port u_ila_1/probe2 [get_nets [list {dac_pulse_period[0]} {dac_pulse_period[1]} {dac_pulse_period[2]} {dac_pulse_period[3]} {dac_pulse_period[4]} {dac_pulse_period[5]} {dac_pulse_period[6]} {dac_pulse_period[7]} {dac_pulse_period[8]} {dac_pulse_period[9]} {dac_pulse_period[10]} {dac_pulse_period[11]} {dac_pulse_period[12]} {dac_pulse_period[13]} {dac_pulse_period[14]} {dac_pulse_period[15]} {dac_pulse_period[16]} {dac_pulse_period[17]} {dac_pulse_period[18]} {dac_pulse_period[19]} {dac_pulse_period[20]} {dac_pulse_period[21]} {dac_pulse_period[22]} {dac_pulse_period[23]} {dac_pulse_period[24]} {dac_pulse_period[25]} {dac_pulse_period[26]} {dac_pulse_period[27]} {dac_pulse_period[28]} {dac_pulse_period[29]} {dac_pulse_period[30]} {dac_pulse_period[31]}]]
|
||||
connect_debug_port u_ila_1/probe3 [get_nets [list {dac_pulse_width[0]} {dac_pulse_width[1]} {dac_pulse_width[2]} {dac_pulse_width[3]} {dac_pulse_width[4]} {dac_pulse_width[5]} {dac_pulse_width[6]} {dac_pulse_width[7]} {dac_pulse_width[8]} {dac_pulse_width[9]} {dac_pulse_width[10]} {dac_pulse_width[11]} {dac_pulse_width[12]} {dac_pulse_width[13]} {dac_pulse_width[14]} {dac_pulse_width[15]} {dac_pulse_width[16]} {dac_pulse_width[17]} {dac_pulse_width[18]} {dac_pulse_width[19]} {dac_pulse_width[20]} {dac_pulse_width[21]} {dac_pulse_width[22]} {dac_pulse_width[23]} {dac_pulse_width[24]} {dac_pulse_width[25]} {dac_pulse_width[26]} {dac_pulse_width[27]} {dac_pulse_width[28]} {dac_pulse_width[29]} {dac_pulse_width[30]} {dac_pulse_width[31]}]]
|
||||
connect_debug_port u_ila_1/probe4 [get_nets [list {generator_inst/cnt_pulse_num[0]} {generator_inst/cnt_pulse_num[1]} {generator_inst/cnt_pulse_num[2]} {generator_inst/cnt_pulse_num[3]} {generator_inst/cnt_pulse_num[4]} {generator_inst/cnt_pulse_num[5]} {generator_inst/cnt_pulse_num[6]} {generator_inst/cnt_pulse_num[7]} {generator_inst/cnt_pulse_num[8]} {generator_inst/cnt_pulse_num[9]} {generator_inst/cnt_pulse_num[10]} {generator_inst/cnt_pulse_num[11]} {generator_inst/cnt_pulse_num[12]} {generator_inst/cnt_pulse_num[13]} {generator_inst/cnt_pulse_num[14]} {generator_inst/cnt_pulse_num[15]}]]
|
||||
connect_debug_port u_ila_1/probe5 [get_nets [list {generator_inst/pulse_width_reg[0]} {generator_inst/pulse_width_reg[1]} {generator_inst/pulse_width_reg[2]} {generator_inst/pulse_width_reg[3]} {generator_inst/pulse_width_reg[4]} {generator_inst/pulse_width_reg[5]} {generator_inst/pulse_width_reg[6]} {generator_inst/pulse_width_reg[7]} {generator_inst/pulse_width_reg[8]} {generator_inst/pulse_width_reg[9]} {generator_inst/pulse_width_reg[10]} {generator_inst/pulse_width_reg[11]} {generator_inst/pulse_width_reg[12]} {generator_inst/pulse_width_reg[13]} {generator_inst/pulse_width_reg[14]} {generator_inst/pulse_width_reg[15]} {generator_inst/pulse_width_reg[16]} {generator_inst/pulse_width_reg[17]} {generator_inst/pulse_width_reg[18]} {generator_inst/pulse_width_reg[19]} {generator_inst/pulse_width_reg[20]} {generator_inst/pulse_width_reg[21]} {generator_inst/pulse_width_reg[22]} {generator_inst/pulse_width_reg[23]} {generator_inst/pulse_width_reg[24]} {generator_inst/pulse_width_reg[25]} {generator_inst/pulse_width_reg[26]} {generator_inst/pulse_width_reg[27]} {generator_inst/pulse_width_reg[28]} {generator_inst/pulse_width_reg[29]} {generator_inst/pulse_width_reg[30]} {generator_inst/pulse_width_reg[31]}]]
|
||||
connect_debug_port u_ila_1/probe6 [get_nets [list {generator_inst/pulse_period_reg[0]} {generator_inst/pulse_period_reg[1]} {generator_inst/pulse_period_reg[2]} {generator_inst/pulse_period_reg[3]} {generator_inst/pulse_period_reg[4]} {generator_inst/pulse_period_reg[5]} {generator_inst/pulse_period_reg[6]} {generator_inst/pulse_period_reg[7]} {generator_inst/pulse_period_reg[8]} {generator_inst/pulse_period_reg[9]} {generator_inst/pulse_period_reg[10]} {generator_inst/pulse_period_reg[11]} {generator_inst/pulse_period_reg[12]} {generator_inst/pulse_period_reg[13]} {generator_inst/pulse_period_reg[14]} {generator_inst/pulse_period_reg[15]} {generator_inst/pulse_period_reg[16]} {generator_inst/pulse_period_reg[17]} {generator_inst/pulse_period_reg[18]} {generator_inst/pulse_period_reg[19]} {generator_inst/pulse_period_reg[20]} {generator_inst/pulse_period_reg[21]} {generator_inst/pulse_period_reg[22]} {generator_inst/pulse_period_reg[23]} {generator_inst/pulse_period_reg[24]} {generator_inst/pulse_period_reg[25]} {generator_inst/pulse_period_reg[26]} {generator_inst/pulse_period_reg[27]} {generator_inst/pulse_period_reg[28]} {generator_inst/pulse_period_reg[29]} {generator_inst/pulse_period_reg[30]} {generator_inst/pulse_period_reg[31]}]]
|
||||
connect_debug_port u_ila_1/probe7 [get_nets [list {generator_inst/cnt_period[0]} {generator_inst/cnt_period[1]} {generator_inst/cnt_period[2]} {generator_inst/cnt_period[3]} {generator_inst/cnt_period[4]} {generator_inst/cnt_period[5]} {generator_inst/cnt_period[6]} {generator_inst/cnt_period[7]} {generator_inst/cnt_period[8]} {generator_inst/cnt_period[9]} {generator_inst/cnt_period[10]} {generator_inst/cnt_period[11]} {generator_inst/cnt_period[12]} {generator_inst/cnt_period[13]} {generator_inst/cnt_period[14]} {generator_inst/cnt_period[15]} {generator_inst/cnt_period[16]} {generator_inst/cnt_period[17]} {generator_inst/cnt_period[18]} {generator_inst/cnt_period[19]} {generator_inst/cnt_period[20]} {generator_inst/cnt_period[21]} {generator_inst/cnt_period[22]} {generator_inst/cnt_period[23]} {generator_inst/cnt_period[24]} {generator_inst/cnt_period[25]} {generator_inst/cnt_period[26]} {generator_inst/cnt_period[27]} {generator_inst/cnt_period[28]} {generator_inst/cnt_period[29]} {generator_inst/cnt_period[30]} {generator_inst/cnt_period[31]}]]
|
||||
connect_debug_port u_ila_1/probe8 [get_nets [list dac_rst]]
|
||||
connect_debug_port u_ila_1/probe9 [get_nets [list dac_start]]
|
||||
connect_debug_port u_ila_1/probe10 [get_nets [list debug_dac_OBUF]]
|
||||
connect_debug_port u_ila_1/probe11 [get_nets [list generator_inst/enable]]
|
||||
connect_debug_port u_ila_1/probe12 [get_nets [list sample_done]]
|
||||
connect_debug_port u_ila_2/clk [get_nets [list rgmii_rxc_IBUF_BUFG]]
|
||||
connect_debug_port u_ila_2/probe0 [get_nets [list {accumulator_top_dut/output_async_fifo/rd_state[0]} {accumulator_top_dut/output_async_fifo/rd_state[1]} {accumulator_top_dut/output_async_fifo/rd_state[2]}]]
|
||||
connect_debug_port dbg_hub/clk [get_nets rgmii_rxc_IBUF_BUFG]
|
||||
|
||||
create_debug_core u_ila_0 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
|
||||
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/clk]
|
||||
connect_debug_port u_ila_0/clk [get_nets [list reflectometer_inst/clk_wiz_ctrl_inst/inst/clk_out2]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe0]
|
||||
connect_debug_port u_ila_0/probe0 [get_nets [list {reflectometer_inst/accumulator_top_dut/accum_main/wr_state[0]} {reflectometer_inst/accumulator_top_dut/accum_main/wr_state[1]} {reflectometer_inst/accumulator_top_dut/accum_main/wr_state[2]} {reflectometer_inst/accumulator_top_dut/accum_main/wr_state[3]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
||||
set_property port_width 3 [get_debug_ports u_ila_0/probe1]
|
||||
connect_debug_port u_ila_0/probe1 [get_nets [list {reflectometer_inst/accumulator_top_dut/output_async_fifo/wr_state[0]} {reflectometer_inst/accumulator_top_dut/output_async_fifo/wr_state[1]} {reflectometer_inst/accumulator_top_dut/output_async_fifo/wr_state[2]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe2]
|
||||
connect_debug_port u_ila_0/probe2 [get_nets [list {reflectometer_inst/sampler_dut/cnt_smp_num[0]} {reflectometer_inst/sampler_dut/cnt_smp_num[1]} {reflectometer_inst/sampler_dut/cnt_smp_num[2]} {reflectometer_inst/sampler_dut/cnt_smp_num[3]} {reflectometer_inst/sampler_dut/cnt_smp_num[4]} {reflectometer_inst/sampler_dut/cnt_smp_num[5]} {reflectometer_inst/sampler_dut/cnt_smp_num[6]} {reflectometer_inst/sampler_dut/cnt_smp_num[7]} {reflectometer_inst/sampler_dut/cnt_smp_num[8]} {reflectometer_inst/sampler_dut/cnt_smp_num[9]} {reflectometer_inst/sampler_dut/cnt_smp_num[10]} {reflectometer_inst/sampler_dut/cnt_smp_num[11]} {reflectometer_inst/sampler_dut/cnt_smp_num[12]} {reflectometer_inst/sampler_dut/cnt_smp_num[13]} {reflectometer_inst/sampler_dut/cnt_smp_num[14]} {reflectometer_inst/sampler_dut/cnt_smp_num[15]} {reflectometer_inst/sampler_dut/cnt_smp_num[16]} {reflectometer_inst/sampler_dut/cnt_smp_num[17]} {reflectometer_inst/sampler_dut/cnt_smp_num[18]} {reflectometer_inst/sampler_dut/cnt_smp_num[19]} {reflectometer_inst/sampler_dut/cnt_smp_num[20]} {reflectometer_inst/sampler_dut/cnt_smp_num[21]} {reflectometer_inst/sampler_dut/cnt_smp_num[22]} {reflectometer_inst/sampler_dut/cnt_smp_num[23]} {reflectometer_inst/sampler_dut/cnt_smp_num[24]} {reflectometer_inst/sampler_dut/cnt_smp_num[25]} {reflectometer_inst/sampler_dut/cnt_smp_num[26]} {reflectometer_inst/sampler_dut/cnt_smp_num[27]} {reflectometer_inst/sampler_dut/cnt_smp_num[28]} {reflectometer_inst/sampler_dut/cnt_smp_num[29]} {reflectometer_inst/sampler_dut/cnt_smp_num[30]} {reflectometer_inst/sampler_dut/cnt_smp_num[31]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
||||
set_property port_width 12 [get_debug_ports u_ila_0/probe3]
|
||||
connect_debug_port u_ila_0/probe3 [get_nets [list {reflectometer_inst/sampler_dut/data_converted[0]} {reflectometer_inst/sampler_dut/data_converted[1]} {reflectometer_inst/sampler_dut/data_converted[2]} {reflectometer_inst/sampler_dut/data_converted[3]} {reflectometer_inst/sampler_dut/data_converted[4]} {reflectometer_inst/sampler_dut/data_converted[5]} {reflectometer_inst/sampler_dut/data_converted[6]} {reflectometer_inst/sampler_dut/data_converted[7]} {reflectometer_inst/sampler_dut/data_converted[8]} {reflectometer_inst/sampler_dut/data_converted[9]} {reflectometer_inst/sampler_dut/data_converted[10]} {reflectometer_inst/sampler_dut/data_converted[11]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe4]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list {reflectometer_inst/sampler_dut/smp_num_reg[0]} {reflectometer_inst/sampler_dut/smp_num_reg[1]} {reflectometer_inst/sampler_dut/smp_num_reg[2]} {reflectometer_inst/sampler_dut/smp_num_reg[3]} {reflectometer_inst/sampler_dut/smp_num_reg[4]} {reflectometer_inst/sampler_dut/smp_num_reg[5]} {reflectometer_inst/sampler_dut/smp_num_reg[6]} {reflectometer_inst/sampler_dut/smp_num_reg[7]} {reflectometer_inst/sampler_dut/smp_num_reg[8]} {reflectometer_inst/sampler_dut/smp_num_reg[9]} {reflectometer_inst/sampler_dut/smp_num_reg[10]} {reflectometer_inst/sampler_dut/smp_num_reg[11]} {reflectometer_inst/sampler_dut/smp_num_reg[12]} {reflectometer_inst/sampler_dut/smp_num_reg[13]} {reflectometer_inst/sampler_dut/smp_num_reg[14]} {reflectometer_inst/sampler_dut/smp_num_reg[15]} {reflectometer_inst/sampler_dut/smp_num_reg[16]} {reflectometer_inst/sampler_dut/smp_num_reg[17]} {reflectometer_inst/sampler_dut/smp_num_reg[18]} {reflectometer_inst/sampler_dut/smp_num_reg[19]} {reflectometer_inst/sampler_dut/smp_num_reg[20]} {reflectometer_inst/sampler_dut/smp_num_reg[21]} {reflectometer_inst/sampler_dut/smp_num_reg[22]} {reflectometer_inst/sampler_dut/smp_num_reg[23]} {reflectometer_inst/sampler_dut/smp_num_reg[24]} {reflectometer_inst/sampler_dut/smp_num_reg[25]} {reflectometer_inst/sampler_dut/smp_num_reg[26]} {reflectometer_inst/sampler_dut/smp_num_reg[27]} {reflectometer_inst/sampler_dut/smp_num_reg[28]} {reflectometer_inst/sampler_dut/smp_num_reg[29]} {reflectometer_inst/sampler_dut/smp_num_reg[30]} {reflectometer_inst/sampler_dut/smp_num_reg[31]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
||||
set_property port_width 12 [get_debug_ports u_ila_0/probe5]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list {reflectometer_inst/accum_m_axis_tdata[0]} {reflectometer_inst/accum_m_axis_tdata[1]} {reflectometer_inst/accum_m_axis_tdata[2]} {reflectometer_inst/accum_m_axis_tdata[3]} {reflectometer_inst/accum_m_axis_tdata[4]} {reflectometer_inst/accum_m_axis_tdata[5]} {reflectometer_inst/accum_m_axis_tdata[6]} {reflectometer_inst/accum_m_axis_tdata[7]} {reflectometer_inst/accum_m_axis_tdata[8]} {reflectometer_inst/accum_m_axis_tdata[9]} {reflectometer_inst/accum_m_axis_tdata[10]} {reflectometer_inst/accum_m_axis_tdata[11]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe6]
|
||||
connect_debug_port u_ila_0/probe6 [get_nets [list {reflectometer_inst/adc_pulse_num[0]} {reflectometer_inst/adc_pulse_num[1]} {reflectometer_inst/adc_pulse_num[2]} {reflectometer_inst/adc_pulse_num[3]} {reflectometer_inst/adc_pulse_num[4]} {reflectometer_inst/adc_pulse_num[5]} {reflectometer_inst/adc_pulse_num[6]} {reflectometer_inst/adc_pulse_num[7]} {reflectometer_inst/adc_pulse_num[8]} {reflectometer_inst/adc_pulse_num[9]} {reflectometer_inst/adc_pulse_num[10]} {reflectometer_inst/adc_pulse_num[11]} {reflectometer_inst/adc_pulse_num[12]} {reflectometer_inst/adc_pulse_num[13]} {reflectometer_inst/adc_pulse_num[14]} {reflectometer_inst/adc_pulse_num[15]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe7]
|
||||
connect_debug_port u_ila_0/probe7 [get_nets [list {reflectometer_inst/adc_pulse_period[0]} {reflectometer_inst/adc_pulse_period[1]} {reflectometer_inst/adc_pulse_period[2]} {reflectometer_inst/adc_pulse_period[3]} {reflectometer_inst/adc_pulse_period[4]} {reflectometer_inst/adc_pulse_period[5]} {reflectometer_inst/adc_pulse_period[6]} {reflectometer_inst/adc_pulse_period[7]} {reflectometer_inst/adc_pulse_period[8]} {reflectometer_inst/adc_pulse_period[9]} {reflectometer_inst/adc_pulse_period[10]} {reflectometer_inst/adc_pulse_period[11]} {reflectometer_inst/adc_pulse_period[12]} {reflectometer_inst/adc_pulse_period[13]} {reflectometer_inst/adc_pulse_period[14]} {reflectometer_inst/adc_pulse_period[15]} {reflectometer_inst/adc_pulse_period[16]} {reflectometer_inst/adc_pulse_period[17]} {reflectometer_inst/adc_pulse_period[18]} {reflectometer_inst/adc_pulse_period[19]} {reflectometer_inst/adc_pulse_period[20]} {reflectometer_inst/adc_pulse_period[21]} {reflectometer_inst/adc_pulse_period[22]} {reflectometer_inst/adc_pulse_period[23]} {reflectometer_inst/adc_pulse_period[24]} {reflectometer_inst/adc_pulse_period[25]} {reflectometer_inst/adc_pulse_period[26]} {reflectometer_inst/adc_pulse_period[27]} {reflectometer_inst/adc_pulse_period[28]} {reflectometer_inst/adc_pulse_period[29]} {reflectometer_inst/adc_pulse_period[30]} {reflectometer_inst/adc_pulse_period[31]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
|
||||
set_property port_width 12 [get_debug_ports u_ila_0/probe8]
|
||||
connect_debug_port u_ila_0/probe8 [get_nets [list {ch2_data_IBUF[0]} {ch2_data_IBUF[1]} {ch2_data_IBUF[2]} {ch2_data_IBUF[3]} {ch2_data_IBUF[4]} {ch2_data_IBUF[5]} {ch2_data_IBUF[6]} {ch2_data_IBUF[7]} {ch2_data_IBUF[8]} {ch2_data_IBUF[9]} {ch2_data_IBUF[10]} {ch2_data_IBUF[11]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
|
||||
connect_debug_port u_ila_0/probe9 [get_nets [list reflectometer_inst/acum_m_axis_tvalid]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
|
||||
connect_debug_port u_ila_0/probe10 [get_nets [list reflectometer_inst/adc_rst]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
|
||||
connect_debug_port u_ila_0/probe11 [get_nets [list reflectometer_inst/adc_start]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
|
||||
connect_debug_port u_ila_0/probe12 [get_nets [list reflectometer_inst/sampler_dut/buffer_ready]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
|
||||
connect_debug_port u_ila_0/probe13 [get_nets [list reflectometer_inst/sampler_dut/enable]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
|
||||
connect_debug_port u_ila_0/probe14 [get_nets [list reflectometer_inst/finish]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
|
||||
connect_debug_port u_ila_0/probe15 [get_nets [list reflectometer_inst/sampler_dut/out_of_range_reg]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
|
||||
connect_debug_port u_ila_0/probe16 [get_nets [list reflectometer_inst/sample_req]]
|
||||
create_debug_core u_ila_1 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1]
|
||||
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/clk]
|
||||
connect_debug_port u_ila_1/clk [get_nets [list reflectometer_inst/clk_wiz_ctrl_inst/inst/clk_out1]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
|
||||
set_property port_width 32 [get_debug_ports u_ila_1/probe0]
|
||||
connect_debug_port u_ila_1/probe0 [get_nets [list {reflectometer_inst/generator_inst/cnt_period[0]} {reflectometer_inst/generator_inst/cnt_period[1]} {reflectometer_inst/generator_inst/cnt_period[2]} {reflectometer_inst/generator_inst/cnt_period[3]} {reflectometer_inst/generator_inst/cnt_period[4]} {reflectometer_inst/generator_inst/cnt_period[5]} {reflectometer_inst/generator_inst/cnt_period[6]} {reflectometer_inst/generator_inst/cnt_period[7]} {reflectometer_inst/generator_inst/cnt_period[8]} {reflectometer_inst/generator_inst/cnt_period[9]} {reflectometer_inst/generator_inst/cnt_period[10]} {reflectometer_inst/generator_inst/cnt_period[11]} {reflectometer_inst/generator_inst/cnt_period[12]} {reflectometer_inst/generator_inst/cnt_period[13]} {reflectometer_inst/generator_inst/cnt_period[14]} {reflectometer_inst/generator_inst/cnt_period[15]} {reflectometer_inst/generator_inst/cnt_period[16]} {reflectometer_inst/generator_inst/cnt_period[17]} {reflectometer_inst/generator_inst/cnt_period[18]} {reflectometer_inst/generator_inst/cnt_period[19]} {reflectometer_inst/generator_inst/cnt_period[20]} {reflectometer_inst/generator_inst/cnt_period[21]} {reflectometer_inst/generator_inst/cnt_period[22]} {reflectometer_inst/generator_inst/cnt_period[23]} {reflectometer_inst/generator_inst/cnt_period[24]} {reflectometer_inst/generator_inst/cnt_period[25]} {reflectometer_inst/generator_inst/cnt_period[26]} {reflectometer_inst/generator_inst/cnt_period[27]} {reflectometer_inst/generator_inst/cnt_period[28]} {reflectometer_inst/generator_inst/cnt_period[29]} {reflectometer_inst/generator_inst/cnt_period[30]} {reflectometer_inst/generator_inst/cnt_period[31]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe1]
|
||||
connect_debug_port u_ila_1/probe1 [get_nets [list {reflectometer_inst/generator_inst/cnt_pulse_num[0]} {reflectometer_inst/generator_inst/cnt_pulse_num[1]} {reflectometer_inst/generator_inst/cnt_pulse_num[2]} {reflectometer_inst/generator_inst/cnt_pulse_num[3]} {reflectometer_inst/generator_inst/cnt_pulse_num[4]} {reflectometer_inst/generator_inst/cnt_pulse_num[5]} {reflectometer_inst/generator_inst/cnt_pulse_num[6]} {reflectometer_inst/generator_inst/cnt_pulse_num[7]} {reflectometer_inst/generator_inst/cnt_pulse_num[8]} {reflectometer_inst/generator_inst/cnt_pulse_num[9]} {reflectometer_inst/generator_inst/cnt_pulse_num[10]} {reflectometer_inst/generator_inst/cnt_pulse_num[11]} {reflectometer_inst/generator_inst/cnt_pulse_num[12]} {reflectometer_inst/generator_inst/cnt_pulse_num[13]} {reflectometer_inst/generator_inst/cnt_pulse_num[14]} {reflectometer_inst/generator_inst/cnt_pulse_num[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2]
|
||||
set_property port_width 14 [get_debug_ports u_ila_1/probe2]
|
||||
connect_debug_port u_ila_1/probe2 [get_nets [list {reflectometer_inst/dac_pulse_height[0]} {reflectometer_inst/dac_pulse_height[1]} {reflectometer_inst/dac_pulse_height[2]} {reflectometer_inst/dac_pulse_height[3]} {reflectometer_inst/dac_pulse_height[4]} {reflectometer_inst/dac_pulse_height[5]} {reflectometer_inst/dac_pulse_height[6]} {reflectometer_inst/dac_pulse_height[7]} {reflectometer_inst/dac_pulse_height[8]} {reflectometer_inst/dac_pulse_height[9]} {reflectometer_inst/dac_pulse_height[10]} {reflectometer_inst/dac_pulse_height[11]} {reflectometer_inst/dac_pulse_height[12]} {reflectometer_inst/dac_pulse_height[13]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3]
|
||||
set_property port_width 32 [get_debug_ports u_ila_1/probe3]
|
||||
connect_debug_port u_ila_1/probe3 [get_nets [list {reflectometer_inst/dac_pulse_width[0]} {reflectometer_inst/dac_pulse_width[1]} {reflectometer_inst/dac_pulse_width[2]} {reflectometer_inst/dac_pulse_width[3]} {reflectometer_inst/dac_pulse_width[4]} {reflectometer_inst/dac_pulse_width[5]} {reflectometer_inst/dac_pulse_width[6]} {reflectometer_inst/dac_pulse_width[7]} {reflectometer_inst/dac_pulse_width[8]} {reflectometer_inst/dac_pulse_width[9]} {reflectometer_inst/dac_pulse_width[10]} {reflectometer_inst/dac_pulse_width[11]} {reflectometer_inst/dac_pulse_width[12]} {reflectometer_inst/dac_pulse_width[13]} {reflectometer_inst/dac_pulse_width[14]} {reflectometer_inst/dac_pulse_width[15]} {reflectometer_inst/dac_pulse_width[16]} {reflectometer_inst/dac_pulse_width[17]} {reflectometer_inst/dac_pulse_width[18]} {reflectometer_inst/dac_pulse_width[19]} {reflectometer_inst/dac_pulse_width[20]} {reflectometer_inst/dac_pulse_width[21]} {reflectometer_inst/dac_pulse_width[22]} {reflectometer_inst/dac_pulse_width[23]} {reflectometer_inst/dac_pulse_width[24]} {reflectometer_inst/dac_pulse_width[25]} {reflectometer_inst/dac_pulse_width[26]} {reflectometer_inst/dac_pulse_width[27]} {reflectometer_inst/dac_pulse_width[28]} {reflectometer_inst/dac_pulse_width[29]} {reflectometer_inst/dac_pulse_width[30]} {reflectometer_inst/dac_pulse_width[31]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4]
|
||||
set_property port_width 16 [get_debug_ports u_ila_1/probe4]
|
||||
connect_debug_port u_ila_1/probe4 [get_nets [list {reflectometer_inst/dac_pulse_num[0]} {reflectometer_inst/dac_pulse_num[1]} {reflectometer_inst/dac_pulse_num[2]} {reflectometer_inst/dac_pulse_num[3]} {reflectometer_inst/dac_pulse_num[4]} {reflectometer_inst/dac_pulse_num[5]} {reflectometer_inst/dac_pulse_num[6]} {reflectometer_inst/dac_pulse_num[7]} {reflectometer_inst/dac_pulse_num[8]} {reflectometer_inst/dac_pulse_num[9]} {reflectometer_inst/dac_pulse_num[10]} {reflectometer_inst/dac_pulse_num[11]} {reflectometer_inst/dac_pulse_num[12]} {reflectometer_inst/dac_pulse_num[13]} {reflectometer_inst/dac_pulse_num[14]} {reflectometer_inst/dac_pulse_num[15]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5]
|
||||
set_property port_width 32 [get_debug_ports u_ila_1/probe5]
|
||||
connect_debug_port u_ila_1/probe5 [get_nets [list {reflectometer_inst/dac_pulse_period[0]} {reflectometer_inst/dac_pulse_period[1]} {reflectometer_inst/dac_pulse_period[2]} {reflectometer_inst/dac_pulse_period[3]} {reflectometer_inst/dac_pulse_period[4]} {reflectometer_inst/dac_pulse_period[5]} {reflectometer_inst/dac_pulse_period[6]} {reflectometer_inst/dac_pulse_period[7]} {reflectometer_inst/dac_pulse_period[8]} {reflectometer_inst/dac_pulse_period[9]} {reflectometer_inst/dac_pulse_period[10]} {reflectometer_inst/dac_pulse_period[11]} {reflectometer_inst/dac_pulse_period[12]} {reflectometer_inst/dac_pulse_period[13]} {reflectometer_inst/dac_pulse_period[14]} {reflectometer_inst/dac_pulse_period[15]} {reflectometer_inst/dac_pulse_period[16]} {reflectometer_inst/dac_pulse_period[17]} {reflectometer_inst/dac_pulse_period[18]} {reflectometer_inst/dac_pulse_period[19]} {reflectometer_inst/dac_pulse_period[20]} {reflectometer_inst/dac_pulse_period[21]} {reflectometer_inst/dac_pulse_period[22]} {reflectometer_inst/dac_pulse_period[23]} {reflectometer_inst/dac_pulse_period[24]} {reflectometer_inst/dac_pulse_period[25]} {reflectometer_inst/dac_pulse_period[26]} {reflectometer_inst/dac_pulse_period[27]} {reflectometer_inst/dac_pulse_period[28]} {reflectometer_inst/dac_pulse_period[29]} {reflectometer_inst/dac_pulse_period[30]} {reflectometer_inst/dac_pulse_period[31]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6]
|
||||
set_property port_width 14 [get_debug_ports u_ila_1/probe6]
|
||||
connect_debug_port u_ila_1/probe6 [get_nets [list {reflectometer_inst/p2_data[0]} {reflectometer_inst/p2_data[1]} {reflectometer_inst/p2_data[2]} {reflectometer_inst/p2_data[3]} {reflectometer_inst/p2_data[4]} {reflectometer_inst/p2_data[5]} {reflectometer_inst/p2_data[6]} {reflectometer_inst/p2_data[7]} {reflectometer_inst/p2_data[8]} {reflectometer_inst/p2_data[9]} {reflectometer_inst/p2_data[10]} {reflectometer_inst/p2_data[11]} {reflectometer_inst/p2_data[12]} {reflectometer_inst/p2_data[13]}]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe7]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe7]
|
||||
connect_debug_port u_ila_1/probe7 [get_nets [list reflectometer_inst/dac_rst]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe8]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe8]
|
||||
connect_debug_port u_ila_1/probe8 [get_nets [list reflectometer_inst/dac_start]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe9]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe9]
|
||||
connect_debug_port u_ila_1/probe9 [get_nets [list reflectometer_inst/generator_inst/enable]]
|
||||
create_debug_port u_ila_1 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe10]
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/probe10]
|
||||
connect_debug_port u_ila_1/probe10 [get_nets [list reflectometer_inst/sample_done]]
|
||||
create_debug_core u_ila_2 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2]
|
||||
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_2]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_2]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_2]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2]
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/clk]
|
||||
connect_debug_port u_ila_2/clk [get_nets [list e_gtxc_OBUF_BUFG]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe0]
|
||||
set_property port_width 8 [get_debug_ports u_ila_2/probe0]
|
||||
connect_debug_port u_ila_2/probe0 [get_nets [list {m_axis_rx_tdata[0]} {m_axis_rx_tdata[1]} {m_axis_rx_tdata[2]} {m_axis_rx_tdata[3]} {m_axis_rx_tdata[4]} {m_axis_rx_tdata[5]} {m_axis_rx_tdata[6]} {m_axis_rx_tdata[7]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe1]
|
||||
set_property port_width 8 [get_debug_ports u_ila_2/probe1]
|
||||
connect_debug_port u_ila_2/probe1 [get_nets [list {s_axis_tx_tdata[0]} {s_axis_tx_tdata[1]} {s_axis_tx_tdata[2]} {s_axis_tx_tdata[3]} {s_axis_tx_tdata[4]} {s_axis_tx_tdata[5]} {s_axis_tx_tdata[6]} {s_axis_tx_tdata[7]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe2]
|
||||
set_property port_width 3 [get_debug_ports u_ila_2/probe2]
|
||||
connect_debug_port u_ila_2/probe2 [get_nets [list {reflectometer_inst/accumulator_top_dut/output_async_fifo/rd_state[0]} {reflectometer_inst/accumulator_top_dut/output_async_fifo/rd_state[1]} {reflectometer_inst/accumulator_top_dut/output_async_fifo/rd_state[2]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe3]
|
||||
set_property port_width 3 [get_debug_ports u_ila_2/probe3]
|
||||
connect_debug_port u_ila_2/probe3 [get_nets [list {reflectometer_inst/udp_ctrl_inst/eth_state[0]} {reflectometer_inst/udp_ctrl_inst/eth_state[1]} {reflectometer_inst/udp_ctrl_inst/eth_state[2]}]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe4]
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/probe4]
|
||||
connect_debug_port u_ila_2/probe4 [get_nets [list reflectometer_inst/udp_ctrl_inst/busy_flag_eth]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe5]
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/probe5]
|
||||
connect_debug_port u_ila_2/probe5 [get_nets [list m_axis_rx_tlast]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe6]
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/probe6]
|
||||
connect_debug_port u_ila_2/probe6 [get_nets [list m_axis_rx_tready]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe7]
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/probe7]
|
||||
connect_debug_port u_ila_2/probe7 [get_nets [list m_axis_rx_tvalid]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe8]
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/probe8]
|
||||
connect_debug_port u_ila_2/probe8 [get_nets [list req_ready]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe9]
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/probe9]
|
||||
connect_debug_port u_ila_2/probe9 [get_nets [list s_axis_tx_tlast]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe10]
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/probe10]
|
||||
connect_debug_port u_ila_2/probe10 [get_nets [list s_axis_tx_tready]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe11]
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/probe11]
|
||||
connect_debug_port u_ila_2/probe11 [get_nets [list s_axis_tx_tvalid]]
|
||||
create_debug_port u_ila_2 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe12]
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/probe12]
|
||||
connect_debug_port u_ila_2/probe12 [get_nets [list send_req]]
|
||||
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
|
||||
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
|
||||
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
|
||||
connect_debug_port dbg_hub/clk [get_nets e_gtxc_OBUF_BUFG]
|
||||
@ -4,7 +4,7 @@
|
||||
"xci_name": "clk_wiz_ctrl_inst",
|
||||
"component_reference": "xilinx.com:ip:clk_wiz:6.0",
|
||||
"ip_revision": "16",
|
||||
"gen_directory": "../../../../eth_ctrl_debug_top.gen/sources_1/ip/clk_wiz_ctrl_inst",
|
||||
"gen_directory": "../../../../eth_generator_top.gen/sources_1/ip/clk_wiz_ctrl_inst",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "clk_wiz_ctrl_inst", "resolve_type": "user", "usage": "all" } ],
|
||||
@ -84,7 +84,7 @@
|
||||
"PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "130.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "65.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
@ -154,9 +154,9 @@
|
||||
"SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_DIVCLK_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_DIVCLK_DIVIDE": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_MULT_F": [ { "value": "4.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_MULT_F": [ { "value": "16.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
@ -167,11 +167,11 @@
|
||||
"MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_DIVIDE_F": [ { "value": "7.500", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_DIVIDE_F": [ { "value": "6.750", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_DIVIDE": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_DIVIDE": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
@ -245,10 +245,10 @@
|
||||
"CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
|
||||
"ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_JITTER": [ { "value": "102.676", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_PHASE_ERROR": [ { "value": "87.159", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_JITTER": [ { "value": "117.878", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_PHASE_ERROR": [ { "value": "87.159", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_JITTER": [ { "value": "162.582", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_PHASE_ERROR": [ { "value": "137.238", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_JITTER": [ { "value": "185.296", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_PHASE_ERROR": [ { "value": "137.238", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
@ -338,14 +338,14 @@
|
||||
"C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__130.00000______0.000______50.0______102.676_____87.159", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__65.00000______0.000______50.0______117.878_____87.159", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__125.00000______0.000______50.0______162.582____137.238", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__64.90385______0.000______50.0______185.296____137.238", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "130.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "125", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "65.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
@ -366,8 +366,8 @@
|
||||
"C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_OUT_FREQ": [ { "value": "130.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_OUT_FREQ": [ { "value": "65.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_OUT_FREQ": [ { "value": "125.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_OUT_FREQ": [ { "value": "64.90385", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
@ -398,18 +398,18 @@
|
||||
"C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_MULT_F": [ { "value": "4.875", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_MULT_F": [ { "value": "16.875", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_DIVCLK_DIVIDE": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "7.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_DIVIDE": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "6.750", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_DIVIDE": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
@ -540,12 +540,12 @@
|
||||
"C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE2_AUTO": [ { "value": "2.0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE3_AUTO": [ { "value": "0.13333333333333333", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE4_AUTO": [ { "value": "0.13333333333333333", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE5_AUTO": [ { "value": "0.13333333333333333", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE6_AUTO": [ { "value": "0.13333333333333333", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE7_AUTO": [ { "value": "0.13333333333333333", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE2_AUTO": [ { "value": "1.9259259259259258", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE3_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE4_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE5_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE6_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE7_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
@ -566,8 +566,8 @@
|
||||
"C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_ACTUAL_FREQ": [ { "value": "130.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_ACTUAL_FREQ": [ { "value": "65.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_ACTUAL_FREQ": [ { "value": "125.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_ACTUAL_FREQ": [ { "value": "64.90385", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
@ -599,7 +599,7 @@
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "16" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../eth_ctrl_debug_top.gen/sources_1/ip/clk_wiz_ctrl_inst" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../eth_generator_top.gen/sources_1/ip/clk_wiz_ctrl_inst" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2025.1" } ],
|
||||
174
designs/reflectometer_prototype/prototype.sv
Normal file
174
designs/reflectometer_prototype/prototype.sv
Normal file
@ -0,0 +1,174 @@
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module prototype_top #(
|
||||
parameter int unsigned DAC_DATA_WIDTH = 14,
|
||||
parameter int unsigned ADC_DATA_WIDTH = 12,
|
||||
parameter PACK_FACTOR = 1,
|
||||
parameter PROCESS_MODE = 0,
|
||||
parameter ZERO_LEVEL = 8192,
|
||||
parameter ACCUM_WIDTH = 32,
|
||||
parameter N_MAX = 4096,
|
||||
parameter WINDOW_SIZE = 65,
|
||||
parameter PACKET_SIZE = 1024
|
||||
)(
|
||||
input sys_clk_p, // system clock positive
|
||||
input sys_clk_n, // system clock negative
|
||||
input rst_n, // reset ,low active
|
||||
output [3:0] led, // display network rate status
|
||||
output e_reset, // phy reset
|
||||
output e_mdc, // phy emdio clock
|
||||
inout e_mdio, // phy emdio data
|
||||
input e_rxc, // 125Mhz ethernet gmii rx clock
|
||||
input e_rxdv, // GMII recieving data valid
|
||||
input e_rxer, // GMII recieving data error
|
||||
input [7:0] e_rxd, // GMII recieving data
|
||||
|
||||
input e_txc, // 25Mhz ethernet mii tx clock
|
||||
output e_gtxc, // 125Mhz ethernet gmii tx clock
|
||||
output e_txen, // GMII sending data valid
|
||||
output e_txer, // GMII sending data error
|
||||
output[7:0] e_txd, // GMII sending data
|
||||
|
||||
// analog
|
||||
output da2_clk,
|
||||
output da2_wrt,
|
||||
output [DAC_DATA_WIDTH-1:0] da2_data,
|
||||
|
||||
output ch2_clk,
|
||||
input ch2_otr,
|
||||
input [ADC_DATA_WIDTH-1:0] ch2_data
|
||||
);
|
||||
|
||||
wire sys_clk; //single end clock
|
||||
wire [31:0] pack_total_len ; //package length
|
||||
wire [1:0] speed ; //net speed select
|
||||
wire link ; //link status
|
||||
wire erxdv ;
|
||||
wire [7:0] erxd ;
|
||||
wire e_tx_en ;
|
||||
wire [7:0] etxd ;
|
||||
wire e_rst_n ;
|
||||
assign e_gtxc = e_rxc;
|
||||
assign e_reset = 1'b1;
|
||||
|
||||
// generate single end clock
|
||||
|
||||
IBUFDS sys_clk_ibufgds
|
||||
(
|
||||
.O (sys_clk ),
|
||||
.I (sys_clk_p ),
|
||||
.IB (sys_clk_n )
|
||||
);
|
||||
|
||||
|
||||
// Different conversion of GMII data according to different network speeds
|
||||
gmii_arbi arbi_inst
|
||||
(
|
||||
.clk (e_gtxc ),
|
||||
.rst_n (rst_n ),
|
||||
.speed (2'b10 ),
|
||||
.link (1'b1 ),
|
||||
.pack_total_len (pack_total_len ),
|
||||
.e_rst_n (e_rst_n ),
|
||||
.gmii_rx_dv (e_rxdv ),
|
||||
.gmii_rxd (e_rxd ),
|
||||
.gmii_tx_en (e_tx_en ),
|
||||
.gmii_txd (etxd ),
|
||||
.e_rx_dv (erxdv ),
|
||||
.e_rxd (erxd ),
|
||||
.e_tx_en (e_txen ),
|
||||
.e_txd (e_txd )
|
||||
);
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// axis_mac interface
|
||||
// ------------------------------------------------------------
|
||||
wire req_ready;
|
||||
|
||||
wire send_req;
|
||||
|
||||
wire [7:0] s_axis_tx_tdata;
|
||||
wire s_axis_tx_tvalid;
|
||||
wire s_axis_tx_tready;
|
||||
wire s_axis_tx_tlast;
|
||||
|
||||
wire [7:0] m_axis_rx_tdata;
|
||||
wire m_axis_rx_tvalid;
|
||||
wire m_axis_rx_tready;
|
||||
wire m_axis_rx_tlast;
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// axis_mac
|
||||
// ------------------------------------------------------------
|
||||
axis_mac axis_mac0
|
||||
(
|
||||
.gmii_tx_clk (e_gtxc),
|
||||
.gmii_rx_clk (e_rxc),
|
||||
.rst_n (e_rst_n),
|
||||
|
||||
.gmii_rx_dv (erxdv),
|
||||
.gmii_rxd (erxd),
|
||||
.gmii_tx_en (e_tx_en),
|
||||
.gmii_txd (etxd),
|
||||
|
||||
.send_req (send_req),
|
||||
.data_length (PACKET_SIZE),
|
||||
.req_ready (req_ready),
|
||||
|
||||
.s_axis_tx_tdata (s_axis_tx_tdata),
|
||||
.s_axis_tx_tvalid (s_axis_tx_tvalid),
|
||||
.s_axis_tx_tready (s_axis_tx_tready),
|
||||
.s_axis_tx_tlast (s_axis_tx_tlast),
|
||||
|
||||
.m_axis_rx_tdata (m_axis_rx_tdata),
|
||||
.m_axis_rx_tvalid (m_axis_rx_tvalid),
|
||||
.m_axis_rx_tready (m_axis_rx_tready),
|
||||
.m_axis_rx_tlast (m_axis_rx_tlast)
|
||||
);
|
||||
|
||||
// reflectometer base module
|
||||
reflectometer_top #(
|
||||
.PROCESS_MODE(PROCESS_MODE),
|
||||
.PACK_FACTOR(PACK_FACTOR),
|
||||
.ACCUM_WIDTH(ACCUM_WIDTH),
|
||||
.N_MAX(N_MAX),
|
||||
.ZERO_LEVEL(ZERO_LEVEL),
|
||||
.WINDOW_SIZE(WINDOW_SIZE),
|
||||
.PACKET_SIZE(PACKET_SIZE),
|
||||
.ADC_DATA_WIDTH(ADC_DATA_WIDTH),
|
||||
.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
|
||||
) reflectometer_inst (
|
||||
.sys_clk (sys_clk),
|
||||
.rst_n (rst_n),
|
||||
|
||||
.led(led),
|
||||
|
||||
.gmii_tx_clk (e_gtxc),
|
||||
.gmii_rx_clk (e_rxc),
|
||||
|
||||
.s_axis_tx_tdata (s_axis_tx_tdata),
|
||||
.s_axis_tx_tvalid (s_axis_tx_tvalid),
|
||||
.s_axis_tx_tready (s_axis_tx_tready),
|
||||
.s_axis_tx_tlast (s_axis_tx_tlast),
|
||||
|
||||
.m_axis_rx_tdata (m_axis_rx_tdata),
|
||||
.m_axis_rx_tvalid (m_axis_rx_tvalid),
|
||||
.m_axis_rx_tready (m_axis_rx_tready),
|
||||
.m_axis_rx_tlast (m_axis_rx_tlast),
|
||||
|
||||
// axis_mac
|
||||
.req_ready(req_ready),
|
||||
.send_req(send_req),
|
||||
|
||||
// DAC
|
||||
.p2_clk(da2_clk),
|
||||
.p2_data(da2_data),
|
||||
.p2_wrt(da2_wrt),
|
||||
|
||||
// ADC
|
||||
.ch2_clk(ch2_clk),
|
||||
.ch2_data(ch2_data),
|
||||
.ch2_otr(ch2_otr)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@ -1 +0,0 @@
|
||||
# Блок Sampler
|
||||
@ -9,7 +9,7 @@ module tb_accumulator_top;
|
||||
localparam PACKET_SIZE = 1024;
|
||||
localparam READ_BATCH_SIZE = (PACKET_SIZE*8)/ACCUM_WIDTH;
|
||||
localparam MAX_WORDS = N_MAX;
|
||||
localparam MAX_SEQ_NUM = 64;
|
||||
localparam MAX_SEQ_NUM = 256;
|
||||
|
||||
logic clk_in;
|
||||
logic eth_clk_in;
|
||||
@ -325,6 +325,9 @@ module tb_accumulator_top;
|
||||
run_test(4, 2, 12 * WINDOW_SIZE, 1'b1, 0, "random_seq7_smp12");
|
||||
run_test(5, 4, 256 * WINDOW_SIZE, 1'b1, 0, "random_max_smpnum");
|
||||
run_test(6, 2, 1500 * WINDOW_SIZE, 1'b1, 0, "random_max_smpnum2");
|
||||
run_test(7, 20, 1 * WINDOW_SIZE, 1'b1, 0, "random_20seq");
|
||||
run_test(8, 20, 3 * WINDOW_SIZE, 1'b1, 0, "random_20seqx3");
|
||||
run_test(9, 200, 1 * WINDOW_SIZE, 1'b1, 0, "random_200seq");
|
||||
|
||||
$display("\n========================================");
|
||||
$display("ALL TESTS COMPLETED");
|
||||
|
||||
@ -11,13 +11,13 @@
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="0.000000 us"></ZoomStartTime>
|
||||
<ZoomEndTime time="16.740001 us"></ZoomEndTime>
|
||||
<Cursor1Time time="6.500000 us"></Cursor1Time>
|
||||
<ZoomStartTime time="2,748,541.000 ns"></ZoomStartTime>
|
||||
<ZoomEndTime time="2,749,382.001 ns"></ZoomEndTime>
|
||||
<Cursor1Time time="2,749,045.000 ns"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="556"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="111"></ValueColumnWidth>
|
||||
<ValueColumnWidth column_width="107"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="18" />
|
||||
<wvobject type="logic" fp_name="/tb_accumulator_top/clk_in">
|
||||
@ -116,6 +116,10 @@
|
||||
<obj_property name="ElementShortName">addrb[15:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">addrb[15:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_accumulator_top/dut/accum_main/wr_state">
|
||||
<obj_property name="ElementShortName">wr_state[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">wr_state[3:0]</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject type="group" fp_name="group27">
|
||||
<obj_property name="label">fifo</obj_property>
|
||||
@ -166,13 +170,13 @@
|
||||
<obj_property name="ObjectShortName">PROG_FULL_THRESH[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_accumulator_top/dut/output_async_fifo/xpm_fifo_async_inst/wr_data_count">
|
||||
<obj_property name="ElementShortName">wr_data_count[4:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">wr_data_count[4:0]</obj_property>
|
||||
<obj_property name="ElementShortName">wr_data_count[9:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">wr_data_count[9:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_accumulator_top/dut/output_async_fifo/xpm_fifo_async_inst/rd_data_count">
|
||||
<obj_property name="ElementShortName">rd_data_count[6:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">rd_data_count[6:0]</obj_property>
|
||||
<obj_property name="ElementShortName">rd_data_count[11:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">rd_data_count[11:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
|
||||
@ -41,14 +41,15 @@
|
||||
|
||||
*start* отправляет пульс start на dac_start и adc_start в их доменах. при этом после этого блок перестает быть ready и ждет, пока не придет пульс finish, после этого он возвращается снова в *idle* состояние
|
||||
|
||||
*set_data* значит, что следующие 96 бит = 12*8 байт, пришедшии по axis - это конфигурационная информация и ее нужно записать в внутренний регистр на 96 бит.
|
||||
*set_data* значит, что следующие 128 бит = 16*8 байт, пришедшии по axis - это конфигурационная информация и ее нужно записать в внутренний регистр на 128 бит.
|
||||
|
||||
конфигурационный регистр на 96 бит делится так:
|
||||
конфигурационный регистр на 128 бит делится так:
|
||||
```
|
||||
reg[31:0] - pulse_width
|
||||
reg[63:32] - pulse_period
|
||||
reg[79:64] - pulse_num
|
||||
reg[79+dac_data_width:80] - pulse_height
|
||||
reg[127:96] - pulse_period_adc
|
||||
```
|
||||
|
||||
соотвественно эти записанные значения выставляются на соотвествующие выходные сигналы в доменах dac_clk и adc_clk. выходы обновляются каждый раз, когда происходит set_data, и сигналы сохраняют своё значение до следующего set_data.
|
||||
|
||||
@ -109,9 +109,11 @@ module control #(
|
||||
// [63:32] pulse_period
|
||||
// [79:64] pulse_num
|
||||
// [95:80] pulse_height_raw[15:0]
|
||||
// [127:96] pulse_period_ADC
|
||||
//
|
||||
// -------------------------------------------------------------------------
|
||||
(* MARK_DEBUG="true" *) logic [95:0] cfg_bus_eth;
|
||||
logic [95:0] cfg_shift_eth;
|
||||
(* MARK_DEBUG="true" *) logic [127:0] cfg_bus_eth;
|
||||
logic [127:0] cfg_shift_eth;
|
||||
|
||||
// ETH-domain parser and control
|
||||
typedef enum logic [2:0] {
|
||||
@ -278,10 +280,10 @@ module control #(
|
||||
// little endian packing
|
||||
cfg_shift_eth[cfg_byte_cnt*8 +: 8] <= s_axis_tdata;
|
||||
|
||||
if (cfg_byte_cnt == 4'd11) begin
|
||||
if (cfg_byte_cnt == 4'd15) begin
|
||||
// this must be the final payload byte
|
||||
if (s_axis_tlast) begin
|
||||
cfg_bus_eth <= {s_axis_tdata, cfg_shift_eth[87:0]};
|
||||
cfg_bus_eth <= {s_axis_tdata, cfg_shift_eth[119:0]};
|
||||
cfg_req_toggle_dac_eth <= ~cfg_req_toggle_dac_eth;
|
||||
cfg_req_toggle_adc_eth <= ~cfg_req_toggle_adc_eth;
|
||||
cfg_wait_dac_ack <= 1'b1;
|
||||
@ -451,7 +453,7 @@ module control #(
|
||||
cfg_req_sync_adc_d <= cfg_req_sync_adc;
|
||||
|
||||
if (cfg_req_pulse_adc) begin
|
||||
adc_pulse_period <= cfg_bus_eth[63:32];
|
||||
adc_pulse_period <= cfg_bus_eth[127:96];
|
||||
adc_pulse_num <= cfg_bus_eth[79:64];
|
||||
|
||||
cfg_ack_toggle_adc <= ~cfg_ack_toggle_adc;
|
||||
|
||||
@ -139,9 +139,10 @@ module tb_control;
|
||||
input logic [31:0] pulse_width,
|
||||
input logic [31:0] pulse_period,
|
||||
input logic [15:0] pulse_num,
|
||||
input logic [15:0] pulse_height_raw
|
||||
input logic [15:0] pulse_height_raw,
|
||||
input logic [31:0] pulse_period_adc
|
||||
);
|
||||
logic [95:0] payload;
|
||||
logic [127:0] payload;
|
||||
int i;
|
||||
begin
|
||||
// little-endian payload layout:
|
||||
@ -149,12 +150,14 @@ module tb_control;
|
||||
// [63:32] pulse_period
|
||||
// [79:64] pulse_num
|
||||
// [95:80] pulse_height_raw
|
||||
payload = {pulse_height_raw, pulse_num, pulse_period, pulse_width};
|
||||
// [127:96] pulse_period_ADC
|
||||
|
||||
payload = {pulse_period_adc, pulse_height_raw, pulse_num, pulse_period, pulse_width};
|
||||
|
||||
axis_send_byte(8'h88, 1'b0); // CMD_SET_DATA
|
||||
|
||||
for (i = 0; i < 12; i++) begin
|
||||
axis_send_byte(payload[i*8 +: 8], (i == 11));
|
||||
for (i = 0; i < 16; i++) begin
|
||||
axis_send_byte(payload[i*8 +: 8], (i == 15));
|
||||
end
|
||||
end
|
||||
endtask
|
||||
@ -219,6 +222,7 @@ module tb_control;
|
||||
input logic [31:0] exp_pulse_period,
|
||||
input logic [15:0] exp_pulse_num,
|
||||
input logic [15:0] exp_pulse_height_raw,
|
||||
input logic [31:0] exp_pulse_period_adc,
|
||||
input int max_cycles = 200
|
||||
);
|
||||
logic [DAC_DATA_WIDTH-1:0] exp_dac_height;
|
||||
@ -232,7 +236,7 @@ module tb_control;
|
||||
(dac_pulse_period === exp_pulse_period) &&
|
||||
(dac_pulse_num === exp_pulse_num ) &&
|
||||
(dac_pulse_height === exp_dac_height ) &&
|
||||
(adc_pulse_period === exp_pulse_period) &&
|
||||
(adc_pulse_period === exp_pulse_period_adc) &&
|
||||
(adc_pulse_num === exp_pulse_num )) begin
|
||||
return;
|
||||
end
|
||||
@ -252,6 +256,7 @@ module tb_control;
|
||||
logic [31:0] test_pulse_period;
|
||||
logic [15:0] test_pulse_num;
|
||||
logic [15:0] test_pulse_height_raw;
|
||||
logic [31:0] test_pulse_period_adc;
|
||||
|
||||
initial begin
|
||||
// defaults
|
||||
@ -265,6 +270,7 @@ module tb_control;
|
||||
test_pulse_period = 32'h55667788;
|
||||
test_pulse_num = 16'hA1B2;
|
||||
test_pulse_height_raw = 16'h0CDE; // for DAC_DATA_WIDTH=12 => 12'hCDE
|
||||
test_pulse_period_adc = 32'h50607080;
|
||||
|
||||
repeat (10) @(posedge eth_clk_in);
|
||||
rst_n = 1'b1;
|
||||
@ -291,14 +297,16 @@ module tb_control;
|
||||
test_pulse_width,
|
||||
test_pulse_period,
|
||||
test_pulse_num,
|
||||
test_pulse_height_raw
|
||||
test_pulse_height_raw,
|
||||
test_pulse_period_adc
|
||||
);
|
||||
|
||||
wait_cfg_applied(
|
||||
test_pulse_width,
|
||||
test_pulse_period,
|
||||
test_pulse_num,
|
||||
test_pulse_height_raw
|
||||
test_pulse_height_raw,
|
||||
test_pulse_period_adc
|
||||
);
|
||||
|
||||
if (dac_pulse_width !== 32'h11223344) begin
|
||||
@ -313,8 +321,8 @@ module tb_control;
|
||||
if (dac_pulse_height !== 12'hCDE) begin
|
||||
$fatal(1, "dac_pulse_height mismatch: got %h expected %h", dac_pulse_height, 12'hCDE);
|
||||
end
|
||||
if (adc_pulse_period !== 32'h55667788) begin
|
||||
$fatal(1, "adc_pulse_period mismatch: got %h expected %h", adc_pulse_period, 32'h55667788);
|
||||
if (adc_pulse_period !== 32'h50607080) begin
|
||||
$fatal(1, "adc_pulse_period mismatch: got %h expected %h", adc_pulse_period, 32'h50607080);
|
||||
end
|
||||
if (adc_pulse_num !== 16'hA1B2) begin
|
||||
$fatal(1, "adc_pulse_num mismatch: got %h expected %h", adc_pulse_num, 16'hA1B2);
|
||||
|
||||
197
rtl/controller/tests/tb_control_behav.wcfg
Normal file
197
rtl/controller/tests/tb_control_behav.wcfg
Normal file
@ -0,0 +1,197 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<wave_config>
|
||||
<wave_state>
|
||||
</wave_state>
|
||||
<db_ref_list>
|
||||
<db_ref path="tb_control_behav.wdb" id="1">
|
||||
<top_modules>
|
||||
<top_module name="glbl" />
|
||||
<top_module name="tb_control" />
|
||||
</top_modules>
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="0.676 ns"></ZoomStartTime>
|
||||
<ZoomEndTime time="645.677 ns"></ZoomEndTime>
|
||||
<Cursor1Time time="349.676 ns"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="558"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="61"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="23" />
|
||||
<wvobject type="logic" fp_name="/tb_control/eth_clk_in">
|
||||
<obj_property name="ElementShortName">eth_clk_in</obj_property>
|
||||
<obj_property name="ObjectShortName">eth_clk_in</obj_property>
|
||||
<obj_property name="CustomSignalColor">#008080</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/dac_clk_in">
|
||||
<obj_property name="ElementShortName">dac_clk_in</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_clk_in</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/adc_clk_in">
|
||||
<obj_property name="ElementShortName">adc_clk_in</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_clk_in</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/rst_n">
|
||||
<obj_property name="ElementShortName">rst_n</obj_property>
|
||||
<obj_property name="ObjectShortName">rst_n</obj_property>
|
||||
<obj_property name="CustomSignalColor">#800080</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/s_axis_tdata">
|
||||
<obj_property name="ElementShortName">s_axis_tdata[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">s_axis_tdata[7:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#008080</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
<obj_property name="Radix">BINARYRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/s_axis_tvalid">
|
||||
<obj_property name="ElementShortName">s_axis_tvalid</obj_property>
|
||||
<obj_property name="ObjectShortName">s_axis_tvalid</obj_property>
|
||||
<obj_property name="CustomSignalColor">#008080</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/s_axis_tready">
|
||||
<obj_property name="ElementShortName">s_axis_tready</obj_property>
|
||||
<obj_property name="ObjectShortName">s_axis_tready</obj_property>
|
||||
<obj_property name="CustomSignalColor">#008080</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/s_axis_tlast">
|
||||
<obj_property name="ElementShortName">s_axis_tlast</obj_property>
|
||||
<obj_property name="ObjectShortName">s_axis_tlast</obj_property>
|
||||
<obj_property name="CustomSignalColor">#008080</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/finish">
|
||||
<obj_property name="ElementShortName">finish</obj_property>
|
||||
<obj_property name="ObjectShortName">finish</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FAAFBE</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/dac_pulse_width">
|
||||
<obj_property name="ElementShortName">dac_pulse_width[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_pulse_width[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/dac_pulse_period">
|
||||
<obj_property name="ElementShortName">dac_pulse_period[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_pulse_period[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/dac_pulse_height">
|
||||
<obj_property name="ElementShortName">dac_pulse_height[11:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_pulse_height[11:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/dac_pulse_num">
|
||||
<obj_property name="ElementShortName">dac_pulse_num[15:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_pulse_num[15:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/adc_pulse_period">
|
||||
<obj_property name="ElementShortName">adc_pulse_period[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_pulse_period[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/adc_pulse_num">
|
||||
<obj_property name="ElementShortName">adc_pulse_num[15:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_pulse_num[15:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/dac_start">
|
||||
<obj_property name="ElementShortName">dac_start</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_start</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/adc_start">
|
||||
<obj_property name="ElementShortName">adc_start</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_start</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/dac_rst">
|
||||
<obj_property name="ElementShortName">dac_rst</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_rst</obj_property>
|
||||
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/adc_rst">
|
||||
<obj_property name="ElementShortName">adc_rst</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_rst</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="group" fp_name="group499">
|
||||
<obj_property name="label">tb signals</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
<wvobject type="array" fp_name="/tb_control/dac_rst_count">
|
||||
<obj_property name="ElementShortName">dac_rst_count[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_rst_count[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/adc_rst_count">
|
||||
<obj_property name="ElementShortName">adc_rst_count[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_rst_count[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/dac_start_count">
|
||||
<obj_property name="ElementShortName">dac_start_count[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">dac_start_count[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/adc_start_count">
|
||||
<obj_property name="ElementShortName">adc_start_count[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">adc_start_count[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/test_pulse_width">
|
||||
<obj_property name="ElementShortName">test_pulse_width[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">test_pulse_width[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/test_pulse_period">
|
||||
<obj_property name="ElementShortName">test_pulse_period[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">test_pulse_period[31:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/test_pulse_num">
|
||||
<obj_property name="ElementShortName">test_pulse_num[15:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">test_pulse_num[15:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/test_pulse_height_raw">
|
||||
<obj_property name="ElementShortName">test_pulse_height_raw[15:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">test_pulse_height_raw[15:0]</obj_property>
|
||||
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/tb_control/DAC_DATA_WIDTH">
|
||||
<obj_property name="ElementShortName">DAC_DATA_WIDTH[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">DAC_DATA_WIDTH[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/dut/cfg_ack_toggle_adc">
|
||||
<obj_property name="ElementShortName">cfg_ack_toggle_adc</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_ack_toggle_adc</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/tb_control/dut/cfg_ack_toggle_dac">
|
||||
<obj_property name="ElementShortName">cfg_ack_toggle_dac</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_ack_toggle_dac</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
@ -283,6 +283,8 @@ module axis_mac
|
||||
reg [31:0] arp_delay;
|
||||
reg arp_cached;
|
||||
|
||||
reg write_en_flag;
|
||||
|
||||
always @(posedge gmii_tx_clk or negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
tx_state <= TX_IDLE;
|
||||
@ -293,8 +295,8 @@ module axis_mac
|
||||
udp_send_data_length <= 16'd0;
|
||||
udp_tx_req <= 1'b0;
|
||||
arp_delay <= 32'b0;
|
||||
write_en_flag <= 1'b0;
|
||||
|
||||
s_axis_tx_tready <= 1'b0;
|
||||
req_ready <= 1'b0;
|
||||
|
||||
tx_req_len <= 16'd0;
|
||||
@ -309,8 +311,8 @@ module axis_mac
|
||||
case (tx_state)
|
||||
// Ready to accept a new packet request
|
||||
TX_IDLE: begin
|
||||
write_en_flag <= 1'b0;
|
||||
udp_tx_req <= 1'b0;
|
||||
s_axis_tx_tready <= 1'b0;
|
||||
tx_bytes_written <= 16'd0;
|
||||
tx_req_inflight <= 1'b0;
|
||||
|
||||
@ -340,7 +342,6 @@ module axis_mac
|
||||
// Pulse ARP request
|
||||
TX_ARP_REQ: begin
|
||||
req_ready <= 1'b0;
|
||||
s_axis_tx_tready <= 1'b0;
|
||||
udp_tx_req <= 1'b0;
|
||||
|
||||
arp_delay <= 32'ha000000;
|
||||
@ -350,7 +351,6 @@ module axis_mac
|
||||
// Wait until ARP is resolved
|
||||
TX_ARP_SEND: begin
|
||||
req_ready <= 1'b0;
|
||||
s_axis_tx_tready <= 1'b0;
|
||||
udp_tx_req <= 1'b0;
|
||||
|
||||
// sent
|
||||
@ -383,7 +383,7 @@ module axis_mac
|
||||
|
||||
if (udp_ram_data_req) begin
|
||||
udp_tx_req <= 1'b0;
|
||||
s_axis_tx_tready <= 1'b1;
|
||||
write_en_flag <= 1'b1;
|
||||
tx_state <= TX_STREAM;
|
||||
end
|
||||
end
|
||||
@ -394,7 +394,6 @@ module axis_mac
|
||||
udp_tx_req <= 1'b0;
|
||||
|
||||
// keep ready high while receiving payload bytes
|
||||
s_axis_tx_tready <= (tx_bytes_written < tx_req_len);
|
||||
|
||||
if (s_axis_tx_tvalid && s_axis_tx_tready) begin
|
||||
tx_ram_wr_data <= s_axis_tx_tdata;
|
||||
@ -403,7 +402,6 @@ module axis_mac
|
||||
tx_bytes_written <= tx_bytes_written + 1'b1;
|
||||
|
||||
if (tx_bytes_written + 1'b1 >= tx_req_len) begin
|
||||
s_axis_tx_tready <= 1'b0;
|
||||
tx_state <= TX_WAIT_DRAIN;
|
||||
end
|
||||
end
|
||||
@ -413,7 +411,8 @@ module axis_mac
|
||||
// Wait until TX RAM starts draining enough to allow
|
||||
// the next request.
|
||||
TX_WAIT_DRAIN: begin
|
||||
s_axis_tx_tready <= 1'b0;
|
||||
// s_axis_tx_tready <= 1'b0;
|
||||
write_en_flag <= 1'b0;
|
||||
udp_tx_req <= 1'b0;
|
||||
|
||||
if (udp_ram_data_count <= tx_release_threshold)
|
||||
@ -425,11 +424,13 @@ module axis_mac
|
||||
tx_state <= TX_IDLE;
|
||||
tx_ram_wr_en <= 1'b0;
|
||||
udp_tx_req <= 1'b0;
|
||||
s_axis_tx_tready <= 1'b0;
|
||||
req_ready <= 1'b0;
|
||||
write_en_flag <= 1'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
assign s_axis_tx_tready = write_en_flag || udp_ram_data_req;
|
||||
|
||||
endmodule
|
||||
@ -4,7 +4,7 @@
|
||||
//Description :
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////////
|
||||
`define TEST_SPEED
|
||||
//`define TEST_SPEED
|
||||
`timescale 1 ns/1 ns
|
||||
module mac_test
|
||||
(
|
||||
|
||||
@ -7,7 +7,7 @@
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xc7a35tfgg484-1
|
||||
FPGA_PART = xc7a100tfgg484-2
|
||||
FPGA_TOP = ethernet_axis_echo
|
||||
FPGA_ARCH = artix7
|
||||
|
||||
@ -23,7 +23,7 @@ SYN_FILES += $(sort $(shell find ../../src -type f \( -name '*.v' -o -name '*.sv
|
||||
XCI_FILES = $(sort $(shell find ../../src -type f -name '*.xci'))
|
||||
|
||||
XDC_FILES += debug.xdc
|
||||
XDC_FILES += ../../../../constraints/ax7a035b.xdc
|
||||
XDC_FILES += ../../../../constraints/ax7102.xdc
|
||||
|
||||
SIM_TOP = tb_mac_test
|
||||
TB_FILES = test_axis_mac_rx.sv
|
||||
|
||||
@ -1,5 +1,36 @@
|
||||
# debug ila
|
||||
|
||||
connect_debug_port u_ila_0/clk [get_nets [list rgmii_rxc_IBUF_BUFG]]
|
||||
connect_debug_port u_ila_0/probe9 [get_nets [list {axis_mac0/udp_rec_data_length[0]} {axis_mac0/udp_rec_data_length[1]} {axis_mac0/udp_rec_data_length[2]} {axis_mac0/udp_rec_data_length[3]} {axis_mac0/udp_rec_data_length[4]} {axis_mac0/udp_rec_data_length[5]} {axis_mac0/udp_rec_data_length[6]} {axis_mac0/udp_rec_data_length[7]} {axis_mac0/udp_rec_data_length[8]} {axis_mac0/udp_rec_data_length[9]} {axis_mac0/udp_rec_data_length[10]} {axis_mac0/udp_rec_data_length[11]} {axis_mac0/udp_rec_data_length[12]} {axis_mac0/udp_rec_data_length[13]} {axis_mac0/udp_rec_data_length[14]} {axis_mac0/udp_rec_data_length[15]}]]
|
||||
connect_debug_port dbg_hub/clk [get_nets rgmii_rxc_IBUF_BUFG]
|
||||
|
||||
connect_debug_port u_ila_0/probe22 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[0]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[1]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[2]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[3]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[4]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[5]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[6]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[7]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[8]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[9]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[10]}]]
|
||||
connect_debug_port u_ila_0/probe23 [get_nets [list {mac_test0/mac_top0/mac_rx0/mac_rx_datain[0]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[1]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[2]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[3]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[4]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[5]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[6]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[7]}]]
|
||||
connect_debug_port u_ila_0/probe24 [get_nets [list {mac_test0/mac_top0/mac_rx0/ip_total_data_length[0]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[1]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[2]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[3]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[4]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[5]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[6]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[7]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[8]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[9]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[10]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[11]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[12]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[13]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[14]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[15]}]]
|
||||
connect_debug_port u_ila_0/probe25 [get_nets [list {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[0]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[1]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[2]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[3]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[4]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[5]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[6]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[7]}]]
|
||||
connect_debug_port u_ila_0/probe26 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[0]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[1]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[2]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[3]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[4]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[5]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[6]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[7]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[8]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[9]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[10]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[11]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[12]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[13]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[14]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[15]}]]
|
||||
connect_debug_port u_ila_0/probe27 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[0]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[1]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[2]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[3]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[4]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[5]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[6]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[7]}]]
|
||||
connect_debug_port u_ila_0/probe28 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[0]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[1]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[2]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[3]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[4]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[5]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[6]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[7]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[8]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[9]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[10]}]]
|
||||
connect_debug_port u_ila_0/probe29 [get_nets [list {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[0]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[1]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[2]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[3]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[4]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[5]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[6]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[7]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[8]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[9]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[10]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[11]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[12]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[13]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[14]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[15]}]]
|
||||
connect_debug_port u_ila_0/probe30 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp0/ck_state[0]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[1]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[2]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[3]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[4]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[5]}]]
|
||||
connect_debug_port u_ila_0/probe31 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp0/state[0]} {mac_test0/mac_top0/mac_tx0/udp0/state[1]} {mac_test0/mac_top0/mac_tx0/udp0/state[2]} {mac_test0/mac_top0/mac_tx0/udp0/state[3]} {mac_test0/mac_top0/mac_tx0/udp0/state[4]} {mac_test0/mac_top0/mac_tx0/udp0/state[5]}]]
|
||||
connect_debug_port u_ila_0/probe32 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp0/usedw[0]} {mac_test0/mac_top0/mac_tx0/udp0/usedw[1]} {mac_test0/mac_top0/mac_tx0/udp0/usedw[2]} {mac_test0/mac_top0/mac_tx0/udp0/usedw[3]}]]
|
||||
connect_debug_port u_ila_0/probe33 [get_nets [list {mac_test0/mac_top0/mac_tx0/mac_tx_data[0]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[1]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[2]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[3]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[4]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[5]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[6]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[7]}]]
|
||||
connect_debug_port u_ila_0/probe34 [get_nets [list {mac_test0/mac_top0/mac_tx0/ram_wr_data[0]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[1]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[2]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[3]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[4]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[5]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[6]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[7]}]]
|
||||
connect_debug_port u_ila_0/probe35 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[0]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[1]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[2]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[3]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[4]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[5]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[6]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[7]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[8]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[9]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[10]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[11]}]]
|
||||
connect_debug_port u_ila_0/probe36 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp_send_data_length[0]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[1]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[2]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[3]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[4]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[5]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[6]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[7]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[8]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[9]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[10]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[11]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[12]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[13]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[14]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[15]}]]
|
||||
connect_debug_port u_ila_0/probe37 [get_nets [list {mac_test0/state[0]} {mac_test0/state[1]} {mac_test0/state[2]} {mac_test0/state[3]} {mac_test0/state[4]} {mac_test0/state[5]} {mac_test0/state[6]} {mac_test0/state[7]} {mac_test0/state[8]}]]
|
||||
connect_debug_port u_ila_0/probe39 [get_nets [list mac_test0/mac_top0/mac_tx0/almost_full]]
|
||||
connect_debug_port u_ila_0/probe45 [get_nets [list mac_test0/mac_top0/mac_tx0/mac_data_valid]]
|
||||
connect_debug_port u_ila_0/probe47 [get_nets [list mac_test0/mac_top0/mac_tx0/mac_send_end]]
|
||||
connect_debug_port u_ila_0/probe48 [get_nets [list mac_test0/mac_top0/mac_tx0/ram_wr_en]]
|
||||
connect_debug_port u_ila_0/probe50 [get_nets [list mac_test0/mac_top0/mac_rx0/udp0/ram_wr_en]]
|
||||
connect_debug_port u_ila_0/probe59 [get_nets [list mac_test0/mac_top0/mac_tx0/udp_ram_data_req]]
|
||||
connect_debug_port u_ila_0/probe62 [get_nets [list mac_test0/mac_top0/mac_rx0/udp_rec_data_valid]]
|
||||
connect_debug_port u_ila_0/probe64 [get_nets [list mac_test0/mac_top0/mac_tx0/udp_tx_end]]
|
||||
connect_debug_port u_ila_0/probe66 [get_nets [list mac_test0/mac_top0/mac_tx0/udp_tx_req]]
|
||||
connect_debug_port u_ila_0/probe68 [get_nets [list mac_test0/mac_top0/mac_tx0/upper_data_req]]
|
||||
|
||||
create_debug_core u_ila_0 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
|
||||
@ -10,251 +41,179 @@ set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/clk]
|
||||
connect_debug_port u_ila_0/clk [get_nets [list rgmii_rxc_IBUF_BUFG]]
|
||||
connect_debug_port u_ila_0/clk [get_nets [list e_gtxc_OBUF_BUFG]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe0]
|
||||
connect_debug_port u_ila_0/probe0 [get_nets [list {arbi_inst/rx_buffer_inst/e10_100_rxd[0]} {arbi_inst/rx_buffer_inst/e10_100_rxd[1]} {arbi_inst/rx_buffer_inst/e10_100_rxd[2]} {arbi_inst/rx_buffer_inst/e10_100_rxd[3]} {arbi_inst/rx_buffer_inst/e10_100_rxd[4]} {arbi_inst/rx_buffer_inst/e10_100_rxd[5]} {arbi_inst/rx_buffer_inst/e10_100_rxd[6]} {arbi_inst/rx_buffer_inst/e10_100_rxd[7]}]]
|
||||
set_property port_width 6 [get_debug_ports u_ila_0/probe0]
|
||||
connect_debug_port u_ila_0/probe0 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp0/state[0]} {axis_mac0/mac_top0/mac_tx0/udp0/state[1]} {axis_mac0/mac_top0/mac_tx0/udp0/state[2]} {axis_mac0/mac_top0/mac_tx0/udp0/state[3]} {axis_mac0/mac_top0/mac_tx0/udp0/state[4]} {axis_mac0/mac_top0/mac_tx0/udp0/state[5]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe1]
|
||||
connect_debug_port u_ila_0/probe1 [get_nets [list {arbi_inst/gmii_rxd[0]} {arbi_inst/gmii_rxd[1]} {arbi_inst/gmii_rxd[2]} {arbi_inst/gmii_rxd[3]} {arbi_inst/gmii_rxd[4]} {arbi_inst/gmii_rxd[5]} {arbi_inst/gmii_rxd[6]} {arbi_inst/gmii_rxd[7]}]]
|
||||
set_property port_width 6 [get_debug_ports u_ila_0/probe1]
|
||||
connect_debug_port u_ila_0/probe1 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[0]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[1]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[2]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[3]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[4]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[5]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe2]
|
||||
connect_debug_port u_ila_0/probe2 [get_nets [list {arbi_inst/gmii_txd[0]} {arbi_inst/gmii_txd[1]} {arbi_inst/gmii_txd[2]} {arbi_inst/gmii_txd[3]} {arbi_inst/gmii_txd[4]} {arbi_inst/gmii_txd[5]} {arbi_inst/gmii_txd[6]} {arbi_inst/gmii_txd[7]}]]
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe2]
|
||||
connect_debug_port u_ila_0/probe2 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp0/usedw[0]} {axis_mac0/mac_top0/mac_tx0/udp0/usedw[1]} {axis_mac0/mac_top0/mac_tx0/udp0/usedw[2]} {axis_mac0/mac_top0/mac_tx0/udp0/usedw[3]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe3]
|
||||
connect_debug_port u_ila_0/probe3 [get_nets [list {arbi_inst/e_txd[0]} {arbi_inst/e_txd[1]} {arbi_inst/e_txd[2]} {arbi_inst/e_txd[3]} {arbi_inst/e_txd[4]} {arbi_inst/e_txd[5]} {arbi_inst/e_txd[6]} {arbi_inst/e_txd[7]}]]
|
||||
connect_debug_port u_ila_0/probe3 [get_nets [list {axis_mac0/s_axis_tx_tdata[0]} {axis_mac0/s_axis_tx_tdata[1]} {axis_mac0/s_axis_tx_tdata[2]} {axis_mac0/s_axis_tx_tdata[3]} {axis_mac0/s_axis_tx_tdata[4]} {axis_mac0/s_axis_tx_tdata[5]} {axis_mac0/s_axis_tx_tdata[6]} {axis_mac0/s_axis_tx_tdata[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe4]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list {arbi_inst/e_rxd[0]} {arbi_inst/e_rxd[1]} {arbi_inst/e_rxd[2]} {arbi_inst/e_rxd[3]} {arbi_inst/e_rxd[4]} {arbi_inst/e_rxd[5]} {arbi_inst/e_rxd[6]} {arbi_inst/e_rxd[7]}]]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe4]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list {axis_mac0/rx_payload_len[0]} {axis_mac0/rx_payload_len[1]} {axis_mac0/rx_payload_len[2]} {axis_mac0/rx_payload_len[3]} {axis_mac0/rx_payload_len[4]} {axis_mac0/rx_payload_len[5]} {axis_mac0/rx_payload_len[6]} {axis_mac0/rx_payload_len[7]} {axis_mac0/rx_payload_len[8]} {axis_mac0/rx_payload_len[9]} {axis_mac0/rx_payload_len[10]} {axis_mac0/rx_payload_len[11]} {axis_mac0/rx_payload_len[12]} {axis_mac0/rx_payload_len[13]} {axis_mac0/rx_payload_len[14]} {axis_mac0/rx_payload_len[15]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe5]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list {arbi_inst/tx_buffer_inst/tx_data_cnt[0]} {arbi_inst/tx_buffer_inst/tx_data_cnt[1]} {arbi_inst/tx_buffer_inst/tx_data_cnt[2]} {arbi_inst/tx_buffer_inst/tx_data_cnt[3]} {arbi_inst/tx_buffer_inst/tx_data_cnt[4]} {arbi_inst/tx_buffer_inst/tx_data_cnt[5]} {arbi_inst/tx_buffer_inst/tx_data_cnt[6]} {arbi_inst/tx_buffer_inst/tx_data_cnt[7]} {arbi_inst/tx_buffer_inst/tx_data_cnt[8]} {arbi_inst/tx_buffer_inst/tx_data_cnt[9]} {arbi_inst/tx_buffer_inst/tx_data_cnt[10]} {arbi_inst/tx_buffer_inst/tx_data_cnt[11]} {arbi_inst/tx_buffer_inst/tx_data_cnt[12]} {arbi_inst/tx_buffer_inst/tx_data_cnt[13]} {arbi_inst/tx_buffer_inst/tx_data_cnt[14]} {arbi_inst/tx_buffer_inst/tx_data_cnt[15]}]]
|
||||
set_property port_width 2 [get_debug_ports u_ila_0/probe5]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list {axis_mac0/rx_state[0]} {axis_mac0/rx_state[1]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe6]
|
||||
connect_debug_port u_ila_0/probe6 [get_nets [list {arbi_inst/tx_buffer_inst/tx_rdata[0]} {arbi_inst/tx_buffer_inst/tx_rdata[1]} {arbi_inst/tx_buffer_inst/tx_rdata[2]} {arbi_inst/tx_buffer_inst/tx_rdata[3]} {arbi_inst/tx_buffer_inst/tx_rdata[4]} {arbi_inst/tx_buffer_inst/tx_rdata[5]} {arbi_inst/tx_buffer_inst/tx_rdata[6]} {arbi_inst/tx_buffer_inst/tx_rdata[7]}]]
|
||||
connect_debug_port u_ila_0/probe6 [get_nets [list {axis_mac0/m_axis_rx_tdata[0]} {axis_mac0/m_axis_rx_tdata[1]} {axis_mac0/m_axis_rx_tdata[2]} {axis_mac0/m_axis_rx_tdata[3]} {axis_mac0/m_axis_rx_tdata[4]} {axis_mac0/m_axis_rx_tdata[5]} {axis_mac0/m_axis_rx_tdata[6]} {axis_mac0/m_axis_rx_tdata[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe7]
|
||||
connect_debug_port u_ila_0/probe7 [get_nets [list {arbi_inst/tx_buffer_inst/tx_wdata[0]} {arbi_inst/tx_buffer_inst/tx_wdata[1]} {arbi_inst/tx_buffer_inst/tx_wdata[2]} {arbi_inst/tx_buffer_inst/tx_wdata[3]} {arbi_inst/tx_buffer_inst/tx_wdata[4]} {arbi_inst/tx_buffer_inst/tx_wdata[5]} {arbi_inst/tx_buffer_inst/tx_wdata[6]} {arbi_inst/tx_buffer_inst/tx_wdata[7]}]]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe7]
|
||||
connect_debug_port u_ila_0/probe7 [get_nets [list {axis_mac0/rx_index[0]} {axis_mac0/rx_index[1]} {axis_mac0/rx_index[2]} {axis_mac0/rx_index[3]} {axis_mac0/rx_index[4]} {axis_mac0/rx_index[5]} {axis_mac0/rx_index[6]} {axis_mac0/rx_index[7]} {axis_mac0/rx_index[8]} {axis_mac0/rx_index[9]} {axis_mac0/rx_index[10]} {axis_mac0/rx_index[11]} {axis_mac0/rx_index[12]} {axis_mac0/rx_index[13]} {axis_mac0/rx_index[14]} {axis_mac0/rx_index[15]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
|
||||
set_property port_width 6 [get_debug_ports u_ila_0/probe8]
|
||||
connect_debug_port u_ila_0/probe8 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[0]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[1]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[2]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[3]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[4]} {axis_mac0/mac_top0/mac_tx0/udp0/ck_state[5]}]]
|
||||
set_property port_width 3 [get_debug_ports u_ila_0/probe8]
|
||||
connect_debug_port u_ila_0/probe8 [get_nets [list {axis_mac0/tx_state[0]} {axis_mac0/tx_state[1]} {axis_mac0/tx_state[2]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe9]
|
||||
connect_debug_port u_ila_0/probe9 [get_nets [list {axis_mac0/udp_rec_data_length[0]} {axis_mac0/udp_rec_data_length[1]} {axis_mac0/udp_rec_data_length[2]} {axis_mac0/udp_rec_data_length[3]} {axis_mac0/udp_rec_data_length[4]} {axis_mac0/udp_rec_data_length[5]} {axis_mac0/udp_rec_data_length[6]} {axis_mac0/udp_rec_data_length[7]} {axis_mac0/udp_rec_data_length[8]} {axis_mac0/udp_rec_data_length[9]} {axis_mac0/udp_rec_data_length[10]} {axis_mac0/udp_rec_data_length[11]} {axis_mac0/udp_rec_data_length[12]} {axis_mac0/udp_rec_data_length[13]} {axis_mac0/udp_rec_data_length[14]} {axis_mac0/udp_rec_data_length[15]}]]
|
||||
set_property port_width 2 [get_debug_ports u_ila_0/probe9]
|
||||
connect_debug_port u_ila_0/probe9 [get_nets [list {test_state[0]} {test_state[1]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
||||
set_property port_width 3 [get_debug_ports u_ila_0/probe10]
|
||||
connect_debug_port u_ila_0/probe10 [get_nets [list {axis_mac0/tx_state[0]} {axis_mac0/tx_state[1]} {axis_mac0/tx_state[2]}]]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe10]
|
||||
connect_debug_port u_ila_0/probe10 [get_nets [list {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[0]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[1]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[2]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[3]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[4]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[5]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[6]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[7]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[8]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[9]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[10]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[11]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[12]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[13]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[14]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[15]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe11]
|
||||
connect_debug_port u_ila_0/probe11 [get_nets [list {axis_mac0/s_axis_tx_tdata[0]} {axis_mac0/s_axis_tx_tdata[1]} {axis_mac0/s_axis_tx_tdata[2]} {axis_mac0/s_axis_tx_tdata[3]} {axis_mac0/s_axis_tx_tdata[4]} {axis_mac0/s_axis_tx_tdata[5]} {axis_mac0/s_axis_tx_tdata[6]} {axis_mac0/s_axis_tx_tdata[7]}]]
|
||||
set_property port_width 11 [get_debug_ports u_ila_0/probe11]
|
||||
connect_debug_port u_ila_0/probe11 [get_nets [list {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[0]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[1]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[2]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[3]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[4]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[5]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[6]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[7]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[8]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[9]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[10]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
||||
set_property port_width 2 [get_debug_ports u_ila_0/probe12]
|
||||
connect_debug_port u_ila_0/probe12 [get_nets [list {axis_mac0/rx_state[0]} {axis_mac0/rx_state[1]}]]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe12]
|
||||
connect_debug_port u_ila_0/probe12 [get_nets [list {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[0]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[1]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[2]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[3]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[4]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[5]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[6]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe13]
|
||||
connect_debug_port u_ila_0/probe13 [get_nets [list {axis_mac0/rx_payload_len[0]} {axis_mac0/rx_payload_len[1]} {axis_mac0/rx_payload_len[2]} {axis_mac0/rx_payload_len[3]} {axis_mac0/rx_payload_len[4]} {axis_mac0/rx_payload_len[5]} {axis_mac0/rx_payload_len[6]} {axis_mac0/rx_payload_len[7]} {axis_mac0/rx_payload_len[8]} {axis_mac0/rx_payload_len[9]} {axis_mac0/rx_payload_len[10]} {axis_mac0/rx_payload_len[11]} {axis_mac0/rx_payload_len[12]} {axis_mac0/rx_payload_len[13]} {axis_mac0/rx_payload_len[14]} {axis_mac0/rx_payload_len[15]}]]
|
||||
connect_debug_port u_ila_0/probe13 [get_nets [list {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[0]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[1]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[2]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[3]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[4]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[5]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[6]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[7]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[8]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[9]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[10]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[11]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[12]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[13]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[14]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[15]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe14]
|
||||
connect_debug_port u_ila_0/probe14 [get_nets [list {axis_mac0/rx_index[0]} {axis_mac0/rx_index[1]} {axis_mac0/rx_index[2]} {axis_mac0/rx_index[3]} {axis_mac0/rx_index[4]} {axis_mac0/rx_index[5]} {axis_mac0/rx_index[6]} {axis_mac0/rx_index[7]} {axis_mac0/rx_index[8]} {axis_mac0/rx_index[9]} {axis_mac0/rx_index[10]} {axis_mac0/rx_index[11]} {axis_mac0/rx_index[12]} {axis_mac0/rx_index[13]} {axis_mac0/rx_index[14]} {axis_mac0/rx_index[15]}]]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe14]
|
||||
connect_debug_port u_ila_0/probe14 [get_nets [list {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[0]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[1]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[2]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[3]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[4]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[5]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[6]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe15]
|
||||
connect_debug_port u_ila_0/probe15 [get_nets [list {axis_mac0/m_axis_rx_tdata[0]} {axis_mac0/m_axis_rx_tdata[1]} {axis_mac0/m_axis_rx_tdata[2]} {axis_mac0/m_axis_rx_tdata[3]} {axis_mac0/m_axis_rx_tdata[4]} {axis_mac0/m_axis_rx_tdata[5]} {axis_mac0/m_axis_rx_tdata[6]} {axis_mac0/m_axis_rx_tdata[7]}]]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe15]
|
||||
connect_debug_port u_ila_0/probe15 [get_nets [list {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[0]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[1]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[2]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[3]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[4]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[5]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[6]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[7]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[8]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[9]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[10]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[11]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[12]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[13]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[14]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[15]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe16]
|
||||
connect_debug_port u_ila_0/probe16 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[0]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[1]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[2]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[3]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[4]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[5]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[6]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[7]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[8]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[9]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[10]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[11]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[12]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[13]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[14]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[15]}]]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe16]
|
||||
connect_debug_port u_ila_0/probe16 [get_nets [list {axis_mac0/mac_top0/mac_tx0/mac_tx_data[0]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[1]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[2]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[3]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[4]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[5]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[6]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
|
||||
set_property port_width 12 [get_debug_ports u_ila_0/probe17]
|
||||
connect_debug_port u_ila_0/probe17 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[0]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[1]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[2]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[3]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[4]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[5]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[6]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[7]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[8]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[9]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[10]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[11]}]]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe17]
|
||||
connect_debug_port u_ila_0/probe17 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[0]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[1]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[2]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[3]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[4]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[5]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[6]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[7]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[8]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[9]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[10]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[11]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[12]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[13]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[14]} {axis_mac0/mac_top0/mac_tx0/udp_send_data_length[15]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe18]
|
||||
connect_debug_port u_ila_0/probe18 [get_nets [list {axis_mac0/mac_top0/mac_tx0/ram_wr_data[0]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[1]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[2]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[3]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[4]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[5]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[6]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[7]}]]
|
||||
set_property port_width 12 [get_debug_ports u_ila_0/probe18]
|
||||
connect_debug_port u_ila_0/probe18 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[0]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[1]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[2]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[3]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[4]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[5]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[6]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[7]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[8]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[9]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[10]} {axis_mac0/mac_top0/mac_tx0/udp_ram_data_count[11]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe19]
|
||||
connect_debug_port u_ila_0/probe19 [get_nets [list {axis_mac0/mac_top0/mac_tx0/mac_tx_data[0]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[1]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[2]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[3]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[4]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[5]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[6]} {axis_mac0/mac_top0/mac_tx0/mac_tx_data[7]}]]
|
||||
connect_debug_port u_ila_0/probe19 [get_nets [list {axis_mac0/mac_top0/mac_tx0/ram_wr_data[0]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[1]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[2]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[3]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[4]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[5]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[6]} {axis_mac0/mac_top0/mac_tx0/ram_wr_data[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe20]
|
||||
connect_debug_port u_ila_0/probe20 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp0/usedw[0]} {axis_mac0/mac_top0/mac_tx0/udp0/usedw[1]} {axis_mac0/mac_top0/mac_tx0/udp0/usedw[2]} {axis_mac0/mac_top0/mac_tx0/udp0/usedw[3]}]]
|
||||
set_property port_width 11 [get_debug_ports u_ila_0/probe20]
|
||||
connect_debug_port u_ila_0/probe20 [get_nets [list {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[0]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[1]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[2]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[3]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[4]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[5]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[6]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[7]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[8]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[9]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[10]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
|
||||
set_property port_width 6 [get_debug_ports u_ila_0/probe21]
|
||||
connect_debug_port u_ila_0/probe21 [get_nets [list {axis_mac0/mac_top0/mac_tx0/udp0/state[0]} {axis_mac0/mac_top0/mac_tx0/udp0/state[1]} {axis_mac0/mac_top0/mac_tx0/udp0/state[2]} {axis_mac0/mac_top0/mac_tx0/udp0/state[3]} {axis_mac0/mac_top0/mac_tx0/udp0/state[4]} {axis_mac0/mac_top0/mac_tx0/udp0/state[5]}]]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe21]
|
||||
connect_debug_port u_ila_0/probe21 [get_nets [list {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[0]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[1]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[2]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[3]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[4]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[5]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[6]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe22]
|
||||
connect_debug_port u_ila_0/probe22 [get_nets [list {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[0]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[1]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[2]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[3]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[4]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[5]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[6]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[7]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[8]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[9]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[10]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[11]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[12]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[13]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[14]} {axis_mac0/mac_top0/mac_rx0/upper_layer_data_length[15]}]]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe22]
|
||||
connect_debug_port u_ila_0/probe22 [get_nets [list axis_mac0/mac_top0/mac_tx0/almost_full]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
|
||||
set_property port_width 11 [get_debug_ports u_ila_0/probe23]
|
||||
connect_debug_port u_ila_0/probe23 [get_nets [list {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[0]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[1]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[2]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[3]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[4]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[5]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[6]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[7]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[8]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[9]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_read_addr[10]}]]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe23]
|
||||
connect_debug_port u_ila_0/probe23 [get_nets [list axis_mac0/arp_found]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe24]
|
||||
connect_debug_port u_ila_0/probe24 [get_nets [list {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[0]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[1]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[2]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[3]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[4]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[5]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[6]} {axis_mac0/mac_top0/mac_rx0/udp_rec_ram_rdata[7]}]]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe24]
|
||||
connect_debug_port u_ila_0/probe24 [get_nets [list axis_mac0/m_axis_rx_tlast]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe25]
|
||||
connect_debug_port u_ila_0/probe25 [get_nets [list {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[0]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[1]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[2]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[3]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[4]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[5]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[6]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[7]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[8]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[9]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[10]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[11]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[12]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[13]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[14]} {axis_mac0/mac_top0/mac_rx0/udp_rec_data_length[15]}]]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe25]
|
||||
connect_debug_port u_ila_0/probe25 [get_nets [list axis_mac0/m_axis_rx_tready]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe26]
|
||||
connect_debug_port u_ila_0/probe26 [get_nets [list {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[0]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[1]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[2]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[3]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[4]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[5]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[6]} {axis_mac0/mac_top0/mac_rx0/mac_rx_dataout[7]}]]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe26]
|
||||
connect_debug_port u_ila_0/probe26 [get_nets [list axis_mac0/m_axis_rx_tvalid]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe27]
|
||||
connect_debug_port u_ila_0/probe27 [get_nets [list {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[0]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[1]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[2]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[3]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[4]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[5]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[6]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[7]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[8]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[9]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[10]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[11]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[12]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[13]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[14]} {axis_mac0/mac_top0/mac_rx0/ip_total_data_length[15]}]]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe27]
|
||||
connect_debug_port u_ila_0/probe27 [get_nets [list axis_mac0/mac_top0/mac_tx0/mac_data_valid]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe28]
|
||||
connect_debug_port u_ila_0/probe28 [get_nets [list {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[0]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[1]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[2]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[3]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[4]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[5]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[6]} {axis_mac0/mac_top0/mac_rx0/mac_rx_datain[7]}]]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe28]
|
||||
connect_debug_port u_ila_0/probe28 [get_nets [list axis_mac0/mac_top0/mac_tx0/mac_send_end]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
|
||||
set_property port_width 11 [get_debug_ports u_ila_0/probe29]
|
||||
connect_debug_port u_ila_0/probe29 [get_nets [list {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[0]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[1]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[2]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[3]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[4]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[5]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[6]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[7]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[8]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[9]} {axis_mac0/mac_top0/mac_rx0/udp0/ram_write_addr[10]}]]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe29]
|
||||
connect_debug_port u_ila_0/probe29 [get_nets [list axis_mac0/mac_top0/mac_rx0/udp0/ram_wr_en]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
|
||||
set_property port_width 2 [get_debug_ports u_ila_0/probe30]
|
||||
connect_debug_port u_ila_0/probe30 [get_nets [list {test_state[0]} {test_state[1]}]]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
|
||||
connect_debug_port u_ila_0/probe30 [get_nets [list axis_mac0/mac_top0/mac_tx0/ram_wr_en]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
|
||||
connect_debug_port u_ila_0/probe31 [get_nets [list axis_mac0/mac_top0/mac_tx0/almost_full]]
|
||||
connect_debug_port u_ila_0/probe31 [get_nets [list req_ready]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
|
||||
connect_debug_port u_ila_0/probe32 [get_nets [list axis_mac0/arp_found]]
|
||||
connect_debug_port u_ila_0/probe32 [get_nets [list axis_mac0/req_ready]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe33]
|
||||
connect_debug_port u_ila_0/probe33 [get_nets [list arbi_inst/rx_buffer_inst/e10_100_rx_dv]]
|
||||
connect_debug_port u_ila_0/probe33 [get_nets [list axis_mac0/s_axis_tx_tlast]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
|
||||
connect_debug_port u_ila_0/probe34 [get_nets [list arbi_inst/e_rx_dv]]
|
||||
connect_debug_port u_ila_0/probe34 [get_nets [list axis_mac0/s_axis_tx_tready]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
|
||||
connect_debug_port u_ila_0/probe35 [get_nets [list arbi_inst/e_tx_en]]
|
||||
connect_debug_port u_ila_0/probe35 [get_nets [list axis_mac0/s_axis_tx_tvalid]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe36]
|
||||
connect_debug_port u_ila_0/probe36 [get_nets [list arbi_inst/gmii_rx_dv]]
|
||||
connect_debug_port u_ila_0/probe36 [get_nets [list send_req]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe37]
|
||||
connect_debug_port u_ila_0/probe37 [get_nets [list arbi_inst/rx_buffer_inst/gmii_rx_dv_d0]]
|
||||
connect_debug_port u_ila_0/probe37 [get_nets [list axis_mac0/send_req]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe38]
|
||||
connect_debug_port u_ila_0/probe38 [get_nets [list arbi_inst/rx_buffer_inst/gmii_rx_dv_d1]]
|
||||
connect_debug_port u_ila_0/probe38 [get_nets [list axis_mac0/mac_top0/mac_tx0/udp_ram_data_req]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe39]
|
||||
connect_debug_port u_ila_0/probe39 [get_nets [list arbi_inst/gmii_tx_en]]
|
||||
connect_debug_port u_ila_0/probe39 [get_nets [list axis_mac0/mac_top0/mac_rx0/udp_rec_data_valid]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe40]
|
||||
connect_debug_port u_ila_0/probe40 [get_nets [list axis_mac0/m_axis_rx_tlast]]
|
||||
connect_debug_port u_ila_0/probe40 [get_nets [list axis_mac0/mac_top0/mac_tx0/udp_tx_end]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe41]
|
||||
connect_debug_port u_ila_0/probe41 [get_nets [list axis_mac0/m_axis_rx_tready]]
|
||||
connect_debug_port u_ila_0/probe41 [get_nets [list axis_mac0/mac_top0/mac_tx0/udp_tx_req]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe42]
|
||||
connect_debug_port u_ila_0/probe42 [get_nets [list axis_mac0/m_axis_rx_tvalid]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe43]
|
||||
connect_debug_port u_ila_0/probe43 [get_nets [list axis_mac0/mac_top0/mac_tx0/mac_data_valid]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe44]
|
||||
connect_debug_port u_ila_0/probe44 [get_nets [list axis_mac0/mac_top0/mac_tx0/mac_send_end]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe45]
|
||||
connect_debug_port u_ila_0/probe45 [get_nets [list axis_mac0/mac_top0/mac_rx0/udp0/ram_wr_en]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe46]
|
||||
connect_debug_port u_ila_0/probe46 [get_nets [list axis_mac0/mac_top0/mac_tx0/ram_wr_en]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe47]
|
||||
connect_debug_port u_ila_0/probe47 [get_nets [list req_ready]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe48]
|
||||
connect_debug_port u_ila_0/probe48 [get_nets [list axis_mac0/req_ready]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe49]
|
||||
connect_debug_port u_ila_0/probe49 [get_nets [list axis_mac0/s_axis_tx_tlast]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe50]
|
||||
connect_debug_port u_ila_0/probe50 [get_nets [list axis_mac0/s_axis_tx_tready]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe51]
|
||||
connect_debug_port u_ila_0/probe51 [get_nets [list axis_mac0/s_axis_tx_tvalid]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe52]
|
||||
connect_debug_port u_ila_0/probe52 [get_nets [list axis_mac0/send_req]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe53]
|
||||
connect_debug_port u_ila_0/probe53 [get_nets [list send_req]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe54]
|
||||
connect_debug_port u_ila_0/probe54 [get_nets [list arbi_inst/tx_buffer_inst/tx_rden]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe55]
|
||||
connect_debug_port u_ila_0/probe55 [get_nets [list arbi_inst/tx_buffer_inst/tx_wren]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe56]
|
||||
connect_debug_port u_ila_0/probe56 [get_nets [list axis_mac0/mac_top0/mac_tx0/udp_ram_data_req]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe57]
|
||||
connect_debug_port u_ila_0/probe57 [get_nets [list axis_mac0/mac_top0/mac_rx0/udp_rec_data_valid]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe58]
|
||||
connect_debug_port u_ila_0/probe58 [get_nets [list axis_mac0/mac_top0/mac_tx0/udp_tx_end]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe59]
|
||||
connect_debug_port u_ila_0/probe59 [get_nets [list axis_mac0/mac_top0/mac_tx0/udp_tx_req]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe60]
|
||||
connect_debug_port u_ila_0/probe60 [get_nets [list axis_mac0/mac_top0/mac_tx0/upper_data_req]]
|
||||
connect_debug_port u_ila_0/probe42 [get_nets [list axis_mac0/mac_top0/mac_tx0/upper_data_req]]
|
||||
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
|
||||
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
|
||||
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
|
||||
connect_debug_port dbg_hub/clk [get_nets rgmii_rxc_IBUF_BUFG]
|
||||
connect_debug_port dbg_hub/clk [get_nets e_gtxc_OBUF_BUFG]
|
||||
|
||||
@ -7,113 +7,63 @@
|
||||
|
||||
module ethernet_axis_echo
|
||||
(
|
||||
input sys_clk_p,
|
||||
input sys_clk_n,
|
||||
input rst_n,
|
||||
output [3:0] led,
|
||||
output e_reset,
|
||||
output e_mdc,
|
||||
inout e_mdio,
|
||||
output [3:0] rgmii_txd,
|
||||
output rgmii_txctl,
|
||||
output rgmii_txc,
|
||||
input [3:0] rgmii_rxd,
|
||||
input rgmii_rxctl,
|
||||
input rgmii_rxc
|
||||
);
|
||||
input sys_clk_p, // system clock positive
|
||||
input sys_clk_n, // system clock negative
|
||||
input rst_n, // reset ,low active
|
||||
output [3:0] led, // display network rate status
|
||||
output e_reset, // phy reset
|
||||
output e_mdc, // phy emdio clock
|
||||
inout e_mdio, // phy emdio data
|
||||
input e_rxc, // 125Mhz ethernet gmii rx clock
|
||||
input e_rxdv, // GMII recieving data valid
|
||||
input e_rxer, // GMII recieving data error
|
||||
input [7:0] e_rxd, // GMII recieving data
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// Internal GMII-side signals
|
||||
// ------------------------------------------------------------
|
||||
wire [7:0] gmii_txd;
|
||||
wire gmii_tx_en;
|
||||
wire gmii_tx_er;
|
||||
wire gmii_tx_clk;
|
||||
wire gmii_crs;
|
||||
wire gmii_col;
|
||||
wire [7:0] gmii_rxd_i;
|
||||
wire gmii_rx_dv;
|
||||
wire gmii_rx_er;
|
||||
wire gmii_rx_clk;
|
||||
input e_txc, // 25Mhz ethernet mii tx clock
|
||||
output e_gtxc, // 125Mhz ethernet gmii tx clock
|
||||
output e_txen, // GMII sending data valid
|
||||
output e_txer, // GMII sending data error
|
||||
output[7:0] e_txd // GMII sending data
|
||||
);
|
||||
wire sys_clk; //single end clock
|
||||
wire [31:0] pack_total_len ; //package length
|
||||
wire [1:0] speed ; //net speed select
|
||||
wire link ; //link status
|
||||
wire erxdv ;
|
||||
wire [7:0] erxd ;
|
||||
wire e_tx_en ;
|
||||
wire [7:0] etxd ;
|
||||
wire e_rst_n ;
|
||||
assign e_gtxc = e_rxc;
|
||||
assign e_reset = 1'b1;
|
||||
|
||||
wire [31:0] pack_total_len;
|
||||
// generate single end clock
|
||||
|
||||
wire e_rx_dv;
|
||||
wire [7:0] e_rxd;
|
||||
wire e_tx_en;
|
||||
wire [7:0] e_txd;
|
||||
wire e_rst_n;
|
||||
wire sys_clk;
|
||||
|
||||
wire duplex_mode;
|
||||
|
||||
assign duplex_mode = 1'b1;
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// System clock buffer
|
||||
// ------------------------------------------------------------
|
||||
IBUFDS sys_clk_ibufgds
|
||||
(
|
||||
.O (sys_clk),
|
||||
.I (sys_clk_p),
|
||||
.IB (sys_clk_n)
|
||||
.O (sys_clk ),
|
||||
.I (sys_clk_p ),
|
||||
.IB (sys_clk_n )
|
||||
);
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// IDELAYCTRL
|
||||
// ------------------------------------------------------------
|
||||
(* IODELAY_GROUP = "rgmii_idelay_group" *)
|
||||
IDELAYCTRL IDELAYCTRL_inst (
|
||||
.RDY(),
|
||||
.REFCLK(sys_clk),
|
||||
.RST(1'b0)
|
||||
);
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// GMII <-> RGMII conversion
|
||||
// ------------------------------------------------------------
|
||||
util_gmii_to_rgmii util_gmii_to_rgmii_m0
|
||||
(
|
||||
.reset (1'b0),
|
||||
.rgmii_td (rgmii_txd),
|
||||
.rgmii_tx_ctl (rgmii_txctl),
|
||||
.rgmii_txc (rgmii_txc),
|
||||
.rgmii_rd (rgmii_rxd),
|
||||
.rgmii_rx_ctl (rgmii_rxctl),
|
||||
.gmii_rx_clk (gmii_rx_clk),
|
||||
.gmii_txd (e_txd),
|
||||
.gmii_tx_en (e_tx_en),
|
||||
.gmii_tx_er (1'b0),
|
||||
.gmii_tx_clk (gmii_tx_clk),
|
||||
.gmii_crs (gmii_crs),
|
||||
.gmii_col (gmii_col),
|
||||
.gmii_rxd (gmii_rxd_i),
|
||||
.rgmii_rxc (rgmii_rxc),
|
||||
.gmii_rx_dv (gmii_rx_dv),
|
||||
.gmii_rx_er (gmii_rx_er),
|
||||
.speed_selection (2'b10),
|
||||
.duplex_mode (duplex_mode)
|
||||
);
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// GMII arbitration / adaptation
|
||||
// ------------------------------------------------------------
|
||||
// Different conversion of GMII data according to different network speeds
|
||||
gmii_arbi arbi_inst
|
||||
(
|
||||
.clk (gmii_tx_clk),
|
||||
.rst_n (rst_n),
|
||||
.speed (2'b10),
|
||||
.link (1'b1),
|
||||
.pack_total_len (pack_total_len),
|
||||
.e_rst_n (e_rst_n),
|
||||
.gmii_rx_dv (gmii_rx_dv),
|
||||
.gmii_rxd (gmii_rxd_i),
|
||||
.gmii_tx_en (gmii_tx_en),
|
||||
.gmii_txd (gmii_txd),
|
||||
.e_rx_dv (e_rx_dv),
|
||||
.e_rxd (e_rxd),
|
||||
.e_tx_en (e_tx_en),
|
||||
.e_txd (e_txd)
|
||||
.clk (e_gtxc ),
|
||||
.rst_n (rst_n ),
|
||||
.speed (2'b10 ),
|
||||
.link (1'b1 ),
|
||||
.pack_total_len (pack_total_len ),
|
||||
.e_rst_n (e_rst_n ),
|
||||
.gmii_rx_dv (e_rxdv ),
|
||||
.gmii_rxd (e_rxd ),
|
||||
.gmii_tx_en (e_tx_en ),
|
||||
.gmii_txd (etxd ),
|
||||
.e_rx_dv (erxdv ),
|
||||
.e_rxd (erxd ),
|
||||
.e_tx_en (e_txen ),
|
||||
.e_txd (e_txd )
|
||||
);
|
||||
|
||||
// ------------------------------------------------------------
|
||||
@ -139,14 +89,14 @@ module ethernet_axis_echo
|
||||
// ------------------------------------------------------------
|
||||
axis_mac axis_mac0
|
||||
(
|
||||
.gmii_tx_clk (gmii_tx_clk),
|
||||
.gmii_rx_clk (gmii_rx_clk),
|
||||
.gmii_tx_clk (e_gtxc),
|
||||
.gmii_rx_clk (e_rxc),
|
||||
.rst_n (e_rst_n),
|
||||
|
||||
.gmii_rx_dv (e_rx_dv),
|
||||
.gmii_rxd (e_rxd),
|
||||
.gmii_tx_en (gmii_tx_en),
|
||||
.gmii_txd (gmii_txd),
|
||||
.gmii_rx_dv (erxdv),
|
||||
.gmii_rxd (erxd),
|
||||
.gmii_tx_en (e_tx_en),
|
||||
.gmii_txd (etxd),
|
||||
|
||||
.send_req (send_req),
|
||||
.data_length (data_length),
|
||||
@ -184,7 +134,7 @@ module ethernet_axis_echo
|
||||
|
||||
assign tx_done_pulse_rx = tx_done_toggle_rx_d1 ^ tx_done_toggle_rx_d0;
|
||||
|
||||
always @(posedge gmii_rx_clk or negedge e_rst_n) begin
|
||||
always @(posedge e_rxc or negedge e_rst_n) begin
|
||||
if (!e_rst_n) begin
|
||||
tx_done_toggle_rx_d0 <= 1'b0;
|
||||
tx_done_toggle_rx_d1 <= 1'b0;
|
||||
@ -194,7 +144,7 @@ module ethernet_axis_echo
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge gmii_rx_clk or negedge e_rst_n) begin
|
||||
always @(posedge e_rxc or negedge e_rst_n) begin
|
||||
if (!e_rst_n) begin
|
||||
rx_wr_ptr <= 16'd0;
|
||||
rx_pkt_len <= 16'd0;
|
||||
@ -227,7 +177,7 @@ module ethernet_axis_echo
|
||||
// sync RX pendind to TX domain
|
||||
reg rx_pkt_pending_tx_d0, rx_pkt_pending_tx_d1;
|
||||
|
||||
always @(posedge gmii_tx_clk or negedge e_rst_n) begin
|
||||
always @(posedge e_gtxc or negedge e_rst_n) begin
|
||||
if (!e_rst_n) begin
|
||||
rx_pkt_pending_tx_d0 <= 1'b0;
|
||||
rx_pkt_pending_tx_d1 <= 1'b0;
|
||||
@ -253,7 +203,7 @@ module ethernet_axis_echo
|
||||
reg [15:0] tx_pkt_len;
|
||||
reg [15:0] tx_rd_ptr;
|
||||
|
||||
always @(posedge gmii_tx_clk or negedge e_rst_n) begin
|
||||
always @(posedge e_gtxc or negedge e_rst_n) begin
|
||||
if (!e_rst_n) begin
|
||||
test_state <= TX_IDLE;
|
||||
tx_busy <= 1'b0;
|
||||
|
||||
@ -7,7 +7,7 @@
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xc7a35tfgg484-1
|
||||
FPGA_PART = xc7a100tfgg484-2
|
||||
FPGA_TOP = ethernet_test_minimal
|
||||
FPGA_ARCH = artix7
|
||||
|
||||
@ -23,7 +23,7 @@ SYN_FILES += $(sort $(shell find ../../src -type f \( -name '*.v' -o -name '*.sv
|
||||
XCI_FILES = $(sort $(shell find ../../src -type f -name '*.xci'))
|
||||
|
||||
XDC_FILES += debug.xdc
|
||||
XDC_FILES += ../../../../constraints/ax7a035b.xdc
|
||||
XDC_FILES += ../../../../constraints/ax7102.xdc
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
|
||||
@ -1,5 +1,8 @@
|
||||
# debug ILA
|
||||
|
||||
connect_debug_port u_ila_0/clk [get_nets [list rgmii_rxc_IBUF_BUFG]]
|
||||
connect_debug_port dbg_hub/clk [get_nets rgmii_rxc_IBUF_BUFG]
|
||||
|
||||
create_debug_core u_ila_0 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
|
||||
@ -10,102 +13,102 @@ set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/clk]
|
||||
connect_debug_port u_ila_0/clk [get_nets [list rgmii_rxc_IBUF_BUFG]]
|
||||
connect_debug_port u_ila_0/clk [get_nets [list e_gtxc_OBUF_BUFG]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
||||
set_property port_width 9 [get_debug_ports u_ila_0/probe0]
|
||||
connect_debug_port u_ila_0/probe0 [get_nets [list {mac_test0/state[0]} {mac_test0/state[1]} {mac_test0/state[2]} {mac_test0/state[3]} {mac_test0/state[4]} {mac_test0/state[5]} {mac_test0/state[6]} {mac_test0/state[7]} {mac_test0/state[8]}]]
|
||||
set_property port_width 11 [get_debug_ports u_ila_0/probe0]
|
||||
connect_debug_port u_ila_0/probe0 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[0]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[1]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[2]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[3]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[4]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[5]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[6]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[7]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[8]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[9]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[10]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe1]
|
||||
connect_debug_port u_ila_0/probe1 [get_nets [list {arbi_inst/rx_buffer_inst/e10_100_rxd[0]} {arbi_inst/rx_buffer_inst/e10_100_rxd[1]} {arbi_inst/rx_buffer_inst/e10_100_rxd[2]} {arbi_inst/rx_buffer_inst/e10_100_rxd[3]} {arbi_inst/rx_buffer_inst/e10_100_rxd[4]} {arbi_inst/rx_buffer_inst/e10_100_rxd[5]} {arbi_inst/rx_buffer_inst/e10_100_rxd[6]} {arbi_inst/rx_buffer_inst/e10_100_rxd[7]}]]
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe1]
|
||||
connect_debug_port u_ila_0/probe1 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp0/usedw[0]} {mac_test0/mac_top0/mac_tx0/udp0/usedw[1]} {mac_test0/mac_top0/mac_tx0/udp0/usedw[2]} {mac_test0/mac_top0/mac_tx0/udp0/usedw[3]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe2]
|
||||
connect_debug_port u_ila_0/probe2 [get_nets [list {arbi_inst/tx_buffer_inst/tx_wdata[0]} {arbi_inst/tx_buffer_inst/tx_wdata[1]} {arbi_inst/tx_buffer_inst/tx_wdata[2]} {arbi_inst/tx_buffer_inst/tx_wdata[3]} {arbi_inst/tx_buffer_inst/tx_wdata[4]} {arbi_inst/tx_buffer_inst/tx_wdata[5]} {arbi_inst/tx_buffer_inst/tx_wdata[6]} {arbi_inst/tx_buffer_inst/tx_wdata[7]}]]
|
||||
set_property port_width 6 [get_debug_ports u_ila_0/probe2]
|
||||
connect_debug_port u_ila_0/probe2 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp0/state[0]} {mac_test0/mac_top0/mac_tx0/udp0/state[1]} {mac_test0/mac_top0/mac_tx0/udp0/state[2]} {mac_test0/mac_top0/mac_tx0/udp0/state[3]} {mac_test0/mac_top0/mac_tx0/udp0/state[4]} {mac_test0/mac_top0/mac_tx0/udp0/state[5]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe3]
|
||||
connect_debug_port u_ila_0/probe3 [get_nets [list {arbi_inst/tx_buffer_inst/tx_rdata[0]} {arbi_inst/tx_buffer_inst/tx_rdata[1]} {arbi_inst/tx_buffer_inst/tx_rdata[2]} {arbi_inst/tx_buffer_inst/tx_rdata[3]} {arbi_inst/tx_buffer_inst/tx_rdata[4]} {arbi_inst/tx_buffer_inst/tx_rdata[5]} {arbi_inst/tx_buffer_inst/tx_rdata[6]} {arbi_inst/tx_buffer_inst/tx_rdata[7]}]]
|
||||
set_property port_width 9 [get_debug_ports u_ila_0/probe3]
|
||||
connect_debug_port u_ila_0/probe3 [get_nets [list {mac_test0/state[0]} {mac_test0/state[1]} {mac_test0/state[2]} {mac_test0/state[3]} {mac_test0/state[4]} {mac_test0/state[5]} {mac_test0/state[6]} {mac_test0/state[7]} {mac_test0/state[8]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe4]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list {arbi_inst/tx_buffer_inst/tx_data_cnt[0]} {arbi_inst/tx_buffer_inst/tx_data_cnt[1]} {arbi_inst/tx_buffer_inst/tx_data_cnt[2]} {arbi_inst/tx_buffer_inst/tx_data_cnt[3]} {arbi_inst/tx_buffer_inst/tx_data_cnt[4]} {arbi_inst/tx_buffer_inst/tx_data_cnt[5]} {arbi_inst/tx_buffer_inst/tx_data_cnt[6]} {arbi_inst/tx_buffer_inst/tx_data_cnt[7]} {arbi_inst/tx_buffer_inst/tx_data_cnt[8]} {arbi_inst/tx_buffer_inst/tx_data_cnt[9]} {arbi_inst/tx_buffer_inst/tx_data_cnt[10]} {arbi_inst/tx_buffer_inst/tx_data_cnt[11]} {arbi_inst/tx_buffer_inst/tx_data_cnt[12]} {arbi_inst/tx_buffer_inst/tx_data_cnt[13]} {arbi_inst/tx_buffer_inst/tx_data_cnt[14]} {arbi_inst/tx_buffer_inst/tx_data_cnt[15]}]]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp_send_data_length[0]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[1]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[2]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[3]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[4]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[5]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[6]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[7]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[8]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[9]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[10]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[11]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[12]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[13]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[14]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[15]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe5]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp_send_data_length[0]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[1]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[2]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[3]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[4]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[5]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[6]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[7]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[8]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[9]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[10]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[11]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[12]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[13]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[14]} {mac_test0/mac_top0/mac_tx0/udp_send_data_length[15]}]]
|
||||
set_property port_width 12 [get_debug_ports u_ila_0/probe5]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[0]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[1]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[2]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[3]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[4]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[5]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[6]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[7]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[8]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[9]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[10]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[11]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
||||
set_property port_width 12 [get_debug_ports u_ila_0/probe6]
|
||||
connect_debug_port u_ila_0/probe6 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[0]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[1]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[2]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[3]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[4]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[5]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[6]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[7]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[8]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[9]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[10]} {mac_test0/mac_top0/mac_tx0/udp_ram_data_count[11]}]]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe6]
|
||||
connect_debug_port u_ila_0/probe6 [get_nets [list {mac_test0/mac_top0/mac_tx0/ram_wr_data[0]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[1]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[2]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[3]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[4]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[5]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[6]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe7]
|
||||
connect_debug_port u_ila_0/probe7 [get_nets [list {mac_test0/mac_top0/mac_tx0/ram_wr_data[0]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[1]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[2]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[3]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[4]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[5]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[6]} {mac_test0/mac_top0/mac_tx0/ram_wr_data[7]}]]
|
||||
connect_debug_port u_ila_0/probe7 [get_nets [list {mac_test0/mac_top0/mac_tx0/mac_tx_data[0]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[1]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[2]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[3]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[4]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[5]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[6]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe8]
|
||||
connect_debug_port u_ila_0/probe8 [get_nets [list {mac_test0/mac_top0/mac_tx0/mac_tx_data[0]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[1]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[2]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[3]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[4]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[5]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[6]} {mac_test0/mac_top0/mac_tx0/mac_tx_data[7]}]]
|
||||
set_property port_width 6 [get_debug_ports u_ila_0/probe8]
|
||||
connect_debug_port u_ila_0/probe8 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp0/ck_state[0]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[1]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[2]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[3]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[4]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[5]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe9]
|
||||
connect_debug_port u_ila_0/probe9 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp0/usedw[0]} {mac_test0/mac_top0/mac_tx0/udp0/usedw[1]} {mac_test0/mac_top0/mac_tx0/udp0/usedw[2]} {mac_test0/mac_top0/mac_tx0/udp0/usedw[3]}]]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe9]
|
||||
connect_debug_port u_ila_0/probe9 [get_nets [list {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[0]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[1]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[2]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[3]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[4]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[5]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[6]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[7]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[8]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[9]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[10]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[11]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[12]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[13]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[14]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[15]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
||||
set_property port_width 6 [get_debug_ports u_ila_0/probe10]
|
||||
connect_debug_port u_ila_0/probe10 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp0/state[0]} {mac_test0/mac_top0/mac_tx0/udp0/state[1]} {mac_test0/mac_top0/mac_tx0/udp0/state[2]} {mac_test0/mac_top0/mac_tx0/udp0/state[3]} {mac_test0/mac_top0/mac_tx0/udp0/state[4]} {mac_test0/mac_top0/mac_tx0/udp0/state[5]}]]
|
||||
set_property port_width 11 [get_debug_ports u_ila_0/probe10]
|
||||
connect_debug_port u_ila_0/probe10 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[0]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[1]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[2]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[3]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[4]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[5]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[6]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[7]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[8]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[9]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[10]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
||||
set_property port_width 6 [get_debug_ports u_ila_0/probe11]
|
||||
connect_debug_port u_ila_0/probe11 [get_nets [list {mac_test0/mac_top0/mac_tx0/udp0/ck_state[0]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[1]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[2]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[3]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[4]} {mac_test0/mac_top0/mac_tx0/udp0/ck_state[5]}]]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe11]
|
||||
connect_debug_port u_ila_0/probe11 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[0]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[1]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[2]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[3]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[4]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[5]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[6]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe12]
|
||||
connect_debug_port u_ila_0/probe12 [get_nets [list {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[0]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[1]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[2]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[3]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[4]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[5]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[6]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[7]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[8]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[9]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[10]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[11]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[12]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[13]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[14]} {mac_test0/mac_top0/mac_rx0/upper_layer_data_length[15]}]]
|
||||
connect_debug_port u_ila_0/probe12 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[0]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[1]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[2]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[3]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[4]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[5]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[6]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[7]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[8]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[9]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[10]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[11]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[12]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[13]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[14]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[15]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
||||
set_property port_width 11 [get_debug_ports u_ila_0/probe13]
|
||||
connect_debug_port u_ila_0/probe13 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[0]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[1]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[2]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[3]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[4]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[5]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[6]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[7]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[8]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[9]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_read_addr[10]}]]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe13]
|
||||
connect_debug_port u_ila_0/probe13 [get_nets [list {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[0]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[1]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[2]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[3]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[4]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[5]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[6]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe14]
|
||||
connect_debug_port u_ila_0/probe14 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[0]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[1]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[2]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[3]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[4]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[5]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[6]} {mac_test0/mac_top0/mac_rx0/udp_rec_ram_rdata[7]}]]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe14]
|
||||
connect_debug_port u_ila_0/probe14 [get_nets [list {mac_test0/mac_top0/mac_rx0/ip_total_data_length[0]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[1]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[2]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[3]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[4]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[5]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[6]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[7]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[8]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[9]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[10]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[11]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[12]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[13]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[14]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[15]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe15]
|
||||
connect_debug_port u_ila_0/probe15 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[0]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[1]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[2]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[3]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[4]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[5]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[6]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[7]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[8]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[9]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[10]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[11]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[12]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[13]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[14]} {mac_test0/mac_top0/mac_rx0/udp_rec_data_length[15]}]]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe15]
|
||||
connect_debug_port u_ila_0/probe15 [get_nets [list {mac_test0/mac_top0/mac_rx0/mac_rx_datain[0]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[1]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[2]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[3]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[4]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[5]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[6]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe16]
|
||||
connect_debug_port u_ila_0/probe16 [get_nets [list {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[0]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[1]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[2]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[3]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[4]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[5]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[6]} {mac_test0/mac_top0/mac_rx0/mac_rx_dataout[7]}]]
|
||||
connect_debug_port u_ila_0/probe16 [get_nets [list {arbi_inst/gmii_txd[0]} {arbi_inst/gmii_txd[1]} {arbi_inst/gmii_txd[2]} {arbi_inst/gmii_txd[3]} {arbi_inst/gmii_txd[4]} {arbi_inst/gmii_txd[5]} {arbi_inst/gmii_txd[6]} {arbi_inst/gmii_txd[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe17]
|
||||
connect_debug_port u_ila_0/probe17 [get_nets [list {mac_test0/mac_top0/mac_rx0/ip_total_data_length[0]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[1]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[2]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[3]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[4]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[5]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[6]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[7]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[8]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[9]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[10]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[11]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[12]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[13]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[14]} {mac_test0/mac_top0/mac_rx0/ip_total_data_length[15]}]]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe17]
|
||||
connect_debug_port u_ila_0/probe17 [get_nets [list {arbi_inst/gmii_rxd[0]} {arbi_inst/gmii_rxd[1]} {arbi_inst/gmii_rxd[2]} {arbi_inst/gmii_rxd[3]} {arbi_inst/gmii_rxd[4]} {arbi_inst/gmii_rxd[5]} {arbi_inst/gmii_rxd[6]} {arbi_inst/gmii_rxd[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe18]
|
||||
connect_debug_port u_ila_0/probe18 [get_nets [list {mac_test0/mac_top0/mac_rx0/mac_rx_datain[0]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[1]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[2]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[3]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[4]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[5]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[6]} {mac_test0/mac_top0/mac_rx0/mac_rx_datain[7]}]]
|
||||
connect_debug_port u_ila_0/probe18 [get_nets [list {arbi_inst/e_txd[0]} {arbi_inst/e_txd[1]} {arbi_inst/e_txd[2]} {arbi_inst/e_txd[3]} {arbi_inst/e_txd[4]} {arbi_inst/e_txd[5]} {arbi_inst/e_txd[6]} {arbi_inst/e_txd[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
|
||||
set_property port_width 11 [get_debug_ports u_ila_0/probe19]
|
||||
connect_debug_port u_ila_0/probe19 [get_nets [list {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[0]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[1]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[2]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[3]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[4]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[5]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[6]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[7]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[8]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[9]} {mac_test0/mac_top0/mac_rx0/udp0/ram_write_addr[10]}]]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe19]
|
||||
connect_debug_port u_ila_0/probe19 [get_nets [list {arbi_inst/e_rxd[0]} {arbi_inst/e_rxd[1]} {arbi_inst/e_rxd[2]} {arbi_inst/e_rxd[3]} {arbi_inst/e_rxd[4]} {arbi_inst/e_rxd[5]} {arbi_inst/e_rxd[6]} {arbi_inst/e_rxd[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe20]
|
||||
connect_debug_port u_ila_0/probe20 [get_nets [list {arbi_inst/gmii_txd[0]} {arbi_inst/gmii_txd[1]} {arbi_inst/gmii_txd[2]} {arbi_inst/gmii_txd[3]} {arbi_inst/gmii_txd[4]} {arbi_inst/gmii_txd[5]} {arbi_inst/gmii_txd[6]} {arbi_inst/gmii_txd[7]}]]
|
||||
connect_debug_port u_ila_0/probe20 [get_nets [list {arbi_inst/tx_buffer_inst/tx_wdata[0]} {arbi_inst/tx_buffer_inst/tx_wdata[1]} {arbi_inst/tx_buffer_inst/tx_wdata[2]} {arbi_inst/tx_buffer_inst/tx_wdata[3]} {arbi_inst/tx_buffer_inst/tx_wdata[4]} {arbi_inst/tx_buffer_inst/tx_wdata[5]} {arbi_inst/tx_buffer_inst/tx_wdata[6]} {arbi_inst/tx_buffer_inst/tx_wdata[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe21]
|
||||
connect_debug_port u_ila_0/probe21 [get_nets [list {arbi_inst/gmii_rxd[0]} {arbi_inst/gmii_rxd[1]} {arbi_inst/gmii_rxd[2]} {arbi_inst/gmii_rxd[3]} {arbi_inst/gmii_rxd[4]} {arbi_inst/gmii_rxd[5]} {arbi_inst/gmii_rxd[6]} {arbi_inst/gmii_rxd[7]}]]
|
||||
connect_debug_port u_ila_0/probe21 [get_nets [list {arbi_inst/tx_buffer_inst/tx_rdata[0]} {arbi_inst/tx_buffer_inst/tx_rdata[1]} {arbi_inst/tx_buffer_inst/tx_rdata[2]} {arbi_inst/tx_buffer_inst/tx_rdata[3]} {arbi_inst/tx_buffer_inst/tx_rdata[4]} {arbi_inst/tx_buffer_inst/tx_rdata[5]} {arbi_inst/tx_buffer_inst/tx_rdata[6]} {arbi_inst/tx_buffer_inst/tx_rdata[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe22]
|
||||
connect_debug_port u_ila_0/probe22 [get_nets [list {arbi_inst/e_txd[0]} {arbi_inst/e_txd[1]} {arbi_inst/e_txd[2]} {arbi_inst/e_txd[3]} {arbi_inst/e_txd[4]} {arbi_inst/e_txd[5]} {arbi_inst/e_txd[6]} {arbi_inst/e_txd[7]}]]
|
||||
set_property port_width 16 [get_debug_ports u_ila_0/probe22]
|
||||
connect_debug_port u_ila_0/probe22 [get_nets [list {arbi_inst/tx_buffer_inst/tx_data_cnt[0]} {arbi_inst/tx_buffer_inst/tx_data_cnt[1]} {arbi_inst/tx_buffer_inst/tx_data_cnt[2]} {arbi_inst/tx_buffer_inst/tx_data_cnt[3]} {arbi_inst/tx_buffer_inst/tx_data_cnt[4]} {arbi_inst/tx_buffer_inst/tx_data_cnt[5]} {arbi_inst/tx_buffer_inst/tx_data_cnt[6]} {arbi_inst/tx_buffer_inst/tx_data_cnt[7]} {arbi_inst/tx_buffer_inst/tx_data_cnt[8]} {arbi_inst/tx_buffer_inst/tx_data_cnt[9]} {arbi_inst/tx_buffer_inst/tx_data_cnt[10]} {arbi_inst/tx_buffer_inst/tx_data_cnt[11]} {arbi_inst/tx_buffer_inst/tx_data_cnt[12]} {arbi_inst/tx_buffer_inst/tx_data_cnt[13]} {arbi_inst/tx_buffer_inst/tx_data_cnt[14]} {arbi_inst/tx_buffer_inst/tx_data_cnt[15]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe23]
|
||||
connect_debug_port u_ila_0/probe23 [get_nets [list {arbi_inst/e_rxd[0]} {arbi_inst/e_rxd[1]} {arbi_inst/e_rxd[2]} {arbi_inst/e_rxd[3]} {arbi_inst/e_rxd[4]} {arbi_inst/e_rxd[5]} {arbi_inst/e_rxd[6]} {arbi_inst/e_rxd[7]}]]
|
||||
connect_debug_port u_ila_0/probe23 [get_nets [list {arbi_inst/rx_buffer_inst/e10_100_rxd[0]} {arbi_inst/rx_buffer_inst/e10_100_rxd[1]} {arbi_inst/rx_buffer_inst/e10_100_rxd[2]} {arbi_inst/rx_buffer_inst/e10_100_rxd[3]} {arbi_inst/rx_buffer_inst/e10_100_rxd[4]} {arbi_inst/rx_buffer_inst/e10_100_rxd[5]} {arbi_inst/rx_buffer_inst/e10_100_rxd[6]} {arbi_inst/rx_buffer_inst/e10_100_rxd[7]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe24]
|
||||
@ -149,11 +152,11 @@ connect_debug_port u_ila_0/probe33 [get_nets [list mac_test0/mac_top0/mac_tx0/ma
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
|
||||
connect_debug_port u_ila_0/probe34 [get_nets [list mac_test0/mac_top0/mac_rx0/udp0/ram_wr_en]]
|
||||
connect_debug_port u_ila_0/probe34 [get_nets [list mac_test0/mac_top0/mac_tx0/ram_wr_en]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
|
||||
connect_debug_port u_ila_0/probe35 [get_nets [list mac_test0/mac_top0/mac_tx0/ram_wr_en]]
|
||||
connect_debug_port u_ila_0/probe35 [get_nets [list mac_test0/mac_top0/mac_rx0/udp0/ram_wr_en]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe36]
|
||||
@ -185,4 +188,4 @@ connect_debug_port u_ila_0/probe42 [get_nets [list mac_test0/mac_top0/mac_tx0/up
|
||||
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
|
||||
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
|
||||
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
|
||||
connect_debug_port dbg_hub/clk [get_nets rgmii_rxc_IBUF_BUFG]
|
||||
connect_debug_port dbg_hub/clk [get_nets e_gtxc_OBUF_BUFG]
|
||||
|
||||
@ -1,134 +1,77 @@
|
||||
module ethernet_test_minimal
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Module Name: ethernet_test
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module ethernet_test
|
||||
(
|
||||
input sys_clk_p, //system clock positive
|
||||
input sys_clk_n, //system clock negative
|
||||
input rst_n, //reset ,low active
|
||||
output [3:0] led, //display network rate status
|
||||
output e_reset, //phy reset
|
||||
output e_mdc, //phy emdio clock
|
||||
inout e_mdio, //phy emdio data
|
||||
output[3:0] rgmii_txd, //phy data send
|
||||
output rgmii_txctl, //phy data send control
|
||||
output rgmii_txc, //Clock for sending data
|
||||
input[3:0] rgmii_rxd, //recieve data
|
||||
input rgmii_rxctl, //Control signal for receiving data
|
||||
input rgmii_rxc //Clock for recieving data
|
||||
input sys_clk_p, // system clock positive
|
||||
input sys_clk_n, // system clock negative
|
||||
input rst_n, // reset ,low active
|
||||
output [3:0] led, // display network rate status
|
||||
output e_reset, // phy reset
|
||||
output e_mdc, // phy emdio clock
|
||||
inout e_mdio, // phy emdio data
|
||||
input e_rxc, // 125Mhz ethernet gmii rx clock
|
||||
input e_rxdv, // GMII recieving data valid
|
||||
input e_rxer, // GMII recieving data error
|
||||
input [7:0] e_rxd, // GMII recieving data
|
||||
|
||||
input e_txc, // 25Mhz ethernet mii tx clock
|
||||
output e_gtxc, // 125Mhz ethernet gmii tx clock
|
||||
output e_txen, // GMII sending data valid
|
||||
output e_txer, // GMII sending data error
|
||||
output[7:0] e_txd // GMII sending data
|
||||
);
|
||||
wire [ 7:0] gmii_txd; //gmii data
|
||||
wire gmii_tx_en; //gmii send enable
|
||||
wire gmii_tx_er;
|
||||
wire gmii_tx_clk; //gmii send clock
|
||||
wire gmii_crs;
|
||||
wire gmii_col;
|
||||
wire [ 7:0] gmii_rxd; //gmii recieving data
|
||||
wire gmii_rx_dv; //gmii recieving data valid
|
||||
wire gmii_rx_er;
|
||||
wire gmii_rx_clk; //gmii recieve clock
|
||||
wire [ 1:0] speed_selection; // 1x gigabit, 01 100Mbps, 00 10mbps
|
||||
wire duplex_mode; // 1 full, 0 half
|
||||
wire rgmii_rxcpll;
|
||||
wire sys_clk; //single end clock
|
||||
wire [31:0] pack_total_len ; //package length
|
||||
wire [1:0] speed ; //net speed select
|
||||
wire link ; //link status
|
||||
wire erxdv ;
|
||||
wire [7:0] erxd ;
|
||||
wire e_tx_en ;
|
||||
wire [7:0] etxd ;
|
||||
wire e_rst_n ;
|
||||
assign e_gtxc = e_rxc;
|
||||
assign e_reset = 1'b1;
|
||||
|
||||
wire [31:0] pack_total_len ; //package length
|
||||
// generate single end clock
|
||||
|
||||
wire [1:0] speed ; //net speed select
|
||||
wire link ; //link status
|
||||
wire e_rx_dv ;
|
||||
wire [7:0] e_rxd ;
|
||||
wire e_tx_en ;
|
||||
wire [7:0] e_txd ;
|
||||
wire e_rst_n ;
|
||||
wire sys_clk ;
|
||||
|
||||
|
||||
assign duplex_mode = 1'b1;
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
generate single end clock
|
||||
**************************************************************************/
|
||||
IBUFDS sys_clk_ibufgds
|
||||
(
|
||||
.O (sys_clk ),
|
||||
.I (sys_clk_p ),
|
||||
.IB (sys_clk_n )
|
||||
);
|
||||
|
||||
(* IODELAY_GROUP = "rgmii_idelay_group" *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
|
||||
|
||||
IDELAYCTRL IDELAYCTRL_inst (
|
||||
.RDY(), // 1-bit output: Ready output
|
||||
.REFCLK(sys_clk), // 1-bit input: Reference clock input
|
||||
.RST(1'b0) // 1-bit input: Active high reset input
|
||||
);
|
||||
/*************************************************************************
|
||||
GMII and RGMII data conversion
|
||||
****************************************************************************/
|
||||
util_gmii_to_rgmii util_gmii_to_rgmii_m0
|
||||
(
|
||||
.reset (1'b0 ),
|
||||
.rgmii_td (rgmii_txd ),
|
||||
.rgmii_tx_ctl (rgmii_txctl ),
|
||||
.rgmii_txc (rgmii_txc ),
|
||||
.rgmii_rd (rgmii_rxd ),
|
||||
.rgmii_rx_ctl (rgmii_rxctl ),
|
||||
.gmii_rx_clk (gmii_rx_clk ),
|
||||
.gmii_txd (e_txd ),
|
||||
.gmii_tx_en (e_tx_en ),
|
||||
.gmii_tx_er (1'b0 ),
|
||||
.gmii_tx_clk (gmii_tx_clk ),
|
||||
.gmii_crs (gmii_crs ),
|
||||
.gmii_col (gmii_col ),
|
||||
.gmii_rxd (gmii_rxd ),
|
||||
.rgmii_rxc (rgmii_rxc ),//add
|
||||
.gmii_rx_dv (gmii_rx_dv ),
|
||||
.gmii_rx_er (gmii_rx_er ),
|
||||
.speed_selection (2'b10 ),
|
||||
.duplex_mode (duplex_mode )
|
||||
);
|
||||
/*************************************************************************
|
||||
Different conversion of GMII data according to different network speeds
|
||||
****************************************************************************/
|
||||
|
||||
gmii_arbi arbi_inst
|
||||
(
|
||||
.clk (gmii_tx_clk ),
|
||||
.rst_n (rst_n ),
|
||||
.speed (2'b10 ),
|
||||
.link (1'b1 ),
|
||||
.pack_total_len (pack_total_len ),
|
||||
.e_rst_n (e_rst_n ),
|
||||
.gmii_rx_dv (gmii_rx_dv ),
|
||||
.gmii_rxd (gmii_rxd ),
|
||||
.gmii_tx_en (gmii_tx_en ),
|
||||
.gmii_txd (gmii_txd ),
|
||||
.e_rx_dv (e_rx_dv ),
|
||||
.e_rxd (e_rxd ),
|
||||
.e_tx_en (e_tx_en ),
|
||||
.e_txd (e_txd )
|
||||
.O (sys_clk ),
|
||||
.I (sys_clk_p ),
|
||||
.IB (sys_clk_n )
|
||||
);
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
Mac layer protocol test
|
||||
****************************************************************************/
|
||||
// Mac layer protocol test
|
||||
mac_test mac_test0
|
||||
(
|
||||
.gmii_tx_clk (gmii_tx_clk ),
|
||||
.gmii_rx_clk (gmii_rx_clk ) ,
|
||||
.rst_n (e_rst_n ),
|
||||
.pack_total_len (pack_total_len ),
|
||||
.gmii_rx_dv (e_rx_dv ),
|
||||
.gmii_rxd (e_rxd ),
|
||||
.gmii_tx_en (gmii_tx_en ),
|
||||
.gmii_txd (gmii_txd )
|
||||
.gmii_tx_clk (e_gtxc ),
|
||||
.gmii_rx_clk (e_rxc ) ,
|
||||
.rst_n (e_rst_n ),
|
||||
.pack_total_len (pack_total_len ),
|
||||
.gmii_rx_dv (erxdv ),
|
||||
.gmii_rxd (erxd ),
|
||||
.gmii_tx_en (e_tx_en ),
|
||||
.gmii_txd (etxd )
|
||||
);
|
||||
/*************************************************************************
|
||||
Generate PHY reset signal
|
||||
****************************************************************************/
|
||||
reset reset_m0
|
||||
|
||||
// Different conversion of GMII data according to different network speeds
|
||||
gmii_arbi arbi_inst
|
||||
(
|
||||
.clk (sys_clk ),
|
||||
.key1 (rst_n ),
|
||||
.rst_n (e_reset )
|
||||
.clk (e_gtxc ),
|
||||
.rst_n (rst_n ),
|
||||
.speed (2'b10 ),
|
||||
.link (1'b1 ),
|
||||
.pack_total_len (pack_total_len ),
|
||||
.e_rst_n (e_rst_n ),
|
||||
.gmii_rx_dv (e_rxdv ),
|
||||
.gmii_rxd (e_rxd ),
|
||||
.gmii_tx_en (e_tx_en ),
|
||||
.gmii_txd (etxd ),
|
||||
.e_rx_dv (erxdv ),
|
||||
.e_rxd (erxd ),
|
||||
.e_tx_en (e_txen ),
|
||||
.e_txd (e_txd )
|
||||
);
|
||||
endmodule
|
||||
|
||||
91
rtl/generator/README.md
Normal file
91
rtl/generator/README.md
Normal file
@ -0,0 +1,91 @@
|
||||
# Генератор
|
||||
|
||||
Модуль выполняет задачу формирования последовательности импульсов заданной амплитуды, длительности и периода.
|
||||
Дополнительно реализован механизм синхронизации с модулем сэмплера через сигналы `sample_req` и `sample_done`, позволяющий запускать сбор данных для каждого импульса и ожидать подтверждения завершения выборки перед переходом к следующему импульсу.
|
||||
|
||||
---
|
||||
|
||||
## Список параметров
|
||||
|
||||
### DATA_WIDTH
|
||||
Ширина выходных данных генератора.
|
||||
|
||||
### ZERO_LEVEL
|
||||
Уровень сигнала в состоянии отсутствия импульса (базовый уровень сигнала).
|
||||
|
||||
Типовые значения:
|
||||
|
||||
- `8192` — середина диапазона ЦАП
|
||||
- `0` — нулевой уровень
|
||||
|
||||
---
|
||||
|
||||
## Список входных портов
|
||||
|
||||
### clk_in
|
||||
Сигнал тактирования модуля.
|
||||
|
||||
### rst
|
||||
Сброс модуля и остановка генерации.
|
||||
|
||||
### start
|
||||
Сигнал запуска последовательности импульсов.
|
||||
|
||||
При его активации модуль фиксирует все входные параметры и начинает генерацию.
|
||||
|
||||
Повторный запуск во время активной генерации блокируется с помощью внутреннего сигнала `enable`.
|
||||
|
||||
### [31:0] pulse_width
|
||||
Длительность активной части импульса (в тактах).
|
||||
|
||||
### [31:0] pulse_period
|
||||
Полный период импульса (в тактах).
|
||||
|
||||
### [DATA_WIDTH-1:0] pulse_height
|
||||
Амплитуда импульса.
|
||||
|
||||
### [15:0] pulse_num
|
||||
Количество импульсов, которое необходимо сгенерировать.
|
||||
|
||||
### sample_done
|
||||
Сигнал подтверждения от сэмплера о завершении выборки данных для текущего импульса.
|
||||
|
||||
---
|
||||
|
||||
## Список выходных портов
|
||||
|
||||
pulse
|
||||
Выходной сигнал разрешения записи сигнала
|
||||
|
||||
[DATA_WIDTH-1:0] pulse_height_out
|
||||
Выходное значение амплитуды сигнала.
|
||||
|
||||
Во время активной части импульса равно `pulse_height`, вне импульса — `ZERO_LEVEL`.
|
||||
|
||||
sample_req
|
||||
Сигнал запроса на запуск выборки в модуле сэмплера.
|
||||
|
||||
Поднимается в начале каждого нового импульса и снимается после получения `sample_done`.
|
||||
|
||||
---
|
||||
|
||||
## Логика работы
|
||||
|
||||
После прихода сигнала `start` модуль:
|
||||
|
||||
- фиксирует входные параметры генерации
|
||||
- сбрасывает внутренние счетчики
|
||||
- поднимает `enable = 1`
|
||||
- формирует первый `sample_req`
|
||||
|
||||
После этого начинается последовательная генерация импульсов.
|
||||
|
||||
---
|
||||
|
||||
## Симуляция
|
||||
Тесты запускаются автоматически через make.
|
||||
```
|
||||
cd tests
|
||||
make sim
|
||||
```
|
||||
При успешном завершении теста высвечивается "ALL PASSED".
|
||||
@ -3,7 +3,8 @@
|
||||
|
||||
module generator
|
||||
#(
|
||||
parameter DATA_WIDTH = 14
|
||||
parameter DATA_WIDTH = 14,
|
||||
parameter ZERO_LEVEL = 8192 // 8192 or 0
|
||||
)
|
||||
(
|
||||
input clk_in,
|
||||
@ -13,81 +14,82 @@ module generator
|
||||
input [31:0] pulse_period,
|
||||
input [DATA_WIDTH-1:0] pulse_height,
|
||||
input [15:0] pulse_num,
|
||||
input sample_done,
|
||||
|
||||
output pulse,
|
||||
output[DATA_WIDTH-1:0] pulse_height_out
|
||||
output[DATA_WIDTH-1:0] pulse_height_out,
|
||||
output logic sample_req
|
||||
|
||||
);
|
||||
|
||||
logic [DATA_WIDTH-1:0] pulse_height_reg, pulse_height_out_reg;
|
||||
logic pulse_reg;
|
||||
(* MARK_DEBUG="true" *) logic [DATA_WIDTH-1:0] pulse_height_reg, pulse_height_out_reg;
|
||||
|
||||
logic [31:0] pulse_width_reg, pulse_period_reg;
|
||||
logic [15:0] pulse_num_reg;
|
||||
(* MARK_DEBUG="true" *) logic [31:0] pulse_width_reg, pulse_period_reg;
|
||||
(* MARK_DEBUG="true" *) logic [15:0] pulse_num_reg;
|
||||
|
||||
logic enable;
|
||||
logic [15:0] cnt_pulse_num;
|
||||
logic [31:0] cnt_period;
|
||||
|
||||
logic start_d;
|
||||
|
||||
always @(posedge clk_in) begin
|
||||
start_d <= start;
|
||||
end
|
||||
|
||||
wire start_pulse = start & ~start_d;
|
||||
(* MARK_DEBUG="true" *) logic enable;
|
||||
(* MARK_DEBUG="true" *) logic [15:0] cnt_pulse_num;
|
||||
(* MARK_DEBUG="true" *) logic [31:0] cnt_period;
|
||||
|
||||
|
||||
always @(posedge clk_in) begin
|
||||
if (rst) begin
|
||||
pulse_reg <= '0;
|
||||
pulse_height_reg <= 0;
|
||||
pulse_height_out_reg <= '0;
|
||||
|
||||
pulse_height_reg <= ZERO_LEVEL;
|
||||
pulse_height_out_reg <= ZERO_LEVEL;
|
||||
pulse_width_reg <= '0;
|
||||
pulse_period_reg <= '0;
|
||||
pulse_num_reg <= '0;
|
||||
enable <= 0;
|
||||
cnt_pulse_num <= '0;
|
||||
cnt_period <= '0;
|
||||
sample_req <= 0;
|
||||
end else begin
|
||||
if (start) begin
|
||||
if (start & !enable) begin
|
||||
enable <= 1'b1;
|
||||
// pulse_width_reg <= pulse_width;
|
||||
// pulse_period_reg <= pulse_period;
|
||||
// pulse_num_reg <= pulse_num;
|
||||
// pulse_height_reg <= pulse_height;
|
||||
|
||||
cnt_pulse_num <= '0;
|
||||
cnt_period <= '0;
|
||||
end
|
||||
if (enable) begin
|
||||
pulse_reg <= 1;
|
||||
|
||||
sample_req <= 1;
|
||||
|
||||
pulse_width_reg <= pulse_width;
|
||||
pulse_period_reg <= pulse_period;
|
||||
pulse_num_reg <= pulse_num;
|
||||
pulse_height_reg <= pulse_height;
|
||||
|
||||
if (pulse_reg) begin
|
||||
|
||||
if (cnt_period < pulse_width_reg) begin
|
||||
pulse_height_out_reg <= pulse_height_reg;
|
||||
end else begin
|
||||
pulse_height_out_reg <= '0;
|
||||
end
|
||||
if (cnt_period == pulse_period_reg - 1) begin
|
||||
cnt_period <= 0;
|
||||
if (cnt_pulse_num == pulse_num_reg - 1) begin
|
||||
enable <= 0;
|
||||
pulse_reg <= 0;
|
||||
end else begin
|
||||
cnt_pulse_num <= cnt_pulse_num + 1;
|
||||
end
|
||||
if (enable) begin
|
||||
|
||||
if (!sample_req && (cnt_period == 0)) begin
|
||||
pulse_height_out_reg <= ZERO_LEVEL;
|
||||
if (sample_done) begin
|
||||
sample_req <= 1'b0;
|
||||
end
|
||||
|
||||
if (!sample_done) begin
|
||||
if (cnt_pulse_num == pulse_num_reg - 1) begin
|
||||
enable <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
cnt_pulse_num <= cnt_pulse_num + 1;
|
||||
sample_req <= 1'b1;
|
||||
cnt_period <= 1;
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
cnt_period <= cnt_period + 1;
|
||||
end
|
||||
|
||||
else begin
|
||||
|
||||
if (cnt_period <= pulse_width_reg) begin
|
||||
pulse_height_out_reg <= pulse_height_reg;
|
||||
end else begin
|
||||
pulse_height_out_reg <= ZERO_LEVEL;
|
||||
end
|
||||
if (cnt_period == pulse_period_reg) begin
|
||||
cnt_period <= 0;
|
||||
end else begin
|
||||
cnt_period <= cnt_period + 1;
|
||||
end
|
||||
if (sample_req && sample_done) begin
|
||||
sample_req <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
@ -3,6 +3,7 @@
|
||||
module generator_tb;
|
||||
|
||||
parameter DATA_WIDTH = 14;
|
||||
parameter ZERO_LEVEL = 8192;
|
||||
parameter CLK_PERIOD = 16;
|
||||
|
||||
logic clk;
|
||||
@ -81,7 +82,7 @@ module generator_tb;
|
||||
|
||||
repeat(40) @(posedge clk);
|
||||
|
||||
pulse_width = 3;
|
||||
pulse_width = 3;
|
||||
pulse_period = 8;
|
||||
pulse_num = 4;
|
||||
pulse_height = 14'h3FF;
|
||||
@ -89,9 +90,17 @@ module generator_tb;
|
||||
|
||||
repeat(1) @(posedge clk);
|
||||
start = 0;
|
||||
|
||||
repeat(5) @(posedge clk);
|
||||
start = 1;
|
||||
pulse_height = 14'h155;
|
||||
|
||||
repeat(1) @(posedge clk);
|
||||
start = 0;
|
||||
|
||||
repeat(50) @(posedge clk);
|
||||
|
||||
|
||||
$display("\n=== TEST FINISHED ===");
|
||||
$finish;
|
||||
end
|
||||
|
||||
@ -1,23 +1,139 @@
|
||||
# Сэмплер
|
||||
Модуль выполняет задачу сбора данных с выхода АЦП, их обработку, упаковку, и передачу дальше с помощью AXI Stream интерфейса.
|
||||
|
||||
## Cписок параметров
|
||||
DATA_WIDTH - ширина входных данных, получаемых с АЦП.
|
||||
PACK_FACTOR - количество отсчетов, собираемых в один выходной пакет.
|
||||
PROCESS_MODE - режим интерпретации входного кода. 0 - прямой код, 1 - дополнительный код.
|
||||
Модуль выполняет задачу сбора данных с выхода АЦП, их обработки, упаковки и передачи дальше с помощью AXI Stream интерфейса.
|
||||
Дополнительно реализован механизм синхронизации с внешним генератором через сигналы `sample_req` и `sample_done`, позволяющий запускать сбор строго по запросу и подтверждать завершение выборки.
|
||||
|
||||
---
|
||||
|
||||
## Список параметров
|
||||
|
||||
DATA_WIDTH
|
||||
Ширина входных данных, получаемых с АЦП.
|
||||
|
||||
PACK_FACTOR
|
||||
Количество отсчетов, собираемых в один выходной пакет.
|
||||
|
||||
PROCESS_MODE
|
||||
Режим интерпретации входного кода:
|
||||
|
||||
- `0` — прямой код
|
||||
- `1` — дополнительный код
|
||||
|
||||
---
|
||||
|
||||
## Список входных портов
|
||||
clk_in - сигнал тактирования выходного интерфейса.
|
||||
rst - сброс модуля и остановка подачи импульсов.
|
||||
[DATA_WIDTH-1:0] data_in - входной сигнал с АЦП.
|
||||
out_of_range - флаг выхода значений данных за допустимый диапазон. 0 - валидны, 1 - не валидны.
|
||||
|
||||
clk_in
|
||||
Сигнал тактирования выходного интерфейса.
|
||||
|
||||
rst
|
||||
Сброс модуля и остановка работы.
|
||||
|
||||
[DATA_WIDTH-1:0] data_in
|
||||
Входной сигнал с АЦП.
|
||||
|
||||
out_of_range
|
||||
Флаг выхода значений данных за допустимый диапазон:
|
||||
|
||||
- `0` — данные валидны
|
||||
- `1` — данные невалидны и игнорируются
|
||||
|
||||
[31:0] smp_num
|
||||
Количество валидных отсчетов, которое необходимо собрать после получения запроса на выборку.
|
||||
|
||||
sample_req
|
||||
Сигнал запроса на запуск выборки.
|
||||
При его активации модуль начинает сбор данных и переходит в активное состояние (`enable = 1`).
|
||||
|
||||
---
|
||||
|
||||
## Список выходных портов
|
||||
[DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata - урезанный axis формат, выходные данные. Ширина шины считается исходя из битности данных и фактора упаковки.
|
||||
m_axis_tvalid - урезанный axis формат, валидность выходных данных.
|
||||
|
||||
[DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata
|
||||
Урезанный AXI Stream формат, выходные данные.
|
||||
Ширина шины определяется как произведение битности данных и фактора упаковки.
|
||||
|
||||
m_axis_tvalid
|
||||
Урезанный AXI Stream формат, сигнал валидности выходных данных.
|
||||
Формируется при готовности очередного пакета.
|
||||
|
||||
sample_done
|
||||
Сигнал завершения выборки.
|
||||
Поднимается после того, как модуль собрал количество валидных отсчетов, равное `smp_num`.
|
||||
|
||||
---
|
||||
|
||||
## Логика работы
|
||||
На каждом такте принимаются data_in (значение АЦП) и out_of_range (флаг выхода значений данных за допустимый диапазон). Если out_of_range = 1, то данные игнорируются и не попадают во внутренний буффер. В противном случае, модуль накапливает данные во внутреннем буффере, идет его заполнение до количества данных, равное PACK_FACTOR. Когда буффер оказывается заполненным, он выдает пакет упакованных данных, сопровождая их импульсом m_axis_tvalid (готовность пакета). Если PROCESS_MODE = 1, данные выдаются в дополнительном коде, если PROCESS_MODE = 0 - в прямом.
|
||||
|
||||
На каждом такте принимаются:
|
||||
|
||||
- `data_in` — значение АЦП
|
||||
- `out_of_range` — флаг допустимости значения
|
||||
|
||||
Если `out_of_range = 1`, данные считаются невалидными, игнорируются и не попадают во внутренний буфер.
|
||||
|
||||
Если `out_of_range = 0`, данные считаются корректными и используются для дальнейшей обработки.
|
||||
|
||||
---
|
||||
|
||||
### Преобразование данных
|
||||
|
||||
Если `PROCESS_MODE = 1`, входные данные интерпретируются как дополнительный код и преобразуются перед упаковкой.
|
||||
|
||||
Если `PROCESS_MODE = 0`, данные передаются без преобразования (прямой код).
|
||||
|
||||
---
|
||||
|
||||
### Запуск выборки
|
||||
|
||||
Сбор данных начинается только после прихода сигнала `sample_req`.
|
||||
|
||||
При этом:
|
||||
|
||||
- фиксируется значение `smp_num`
|
||||
- внутренний счетчик собранных отсчетов обнуляется
|
||||
- модуль переходит в активное состояние (`enable = 1`)
|
||||
|
||||
Пока `enable = 1`, модуль принимает только валидные отсчеты и считает их.
|
||||
|
||||
---
|
||||
|
||||
### Упаковка данных
|
||||
|
||||
Внутренний буфер заполняется до количества данных, равного `PACK_FACTOR`.
|
||||
|
||||
#### Если `PACK_FACTOR = 1`
|
||||
|
||||
Каждый валидный отсчет сразу формирует выходной пакет:
|
||||
|
||||
- данные передаются в `m_axis_tdata`
|
||||
- формируется импульс `m_axis_tvalid`
|
||||
|
||||
#### Если `PACK_FACTOR > 1`
|
||||
|
||||
Данные последовательно накапливаются во внутреннем сдвиговом буфере.
|
||||
|
||||
Когда буфер полностью заполнен:
|
||||
|
||||
- формируется пакет упакованных данных
|
||||
- поднимается `m_axis_tvalid`
|
||||
|
||||
После этого начинается сбор следующего пакета.
|
||||
|
||||
---
|
||||
|
||||
### Завершение выборки
|
||||
|
||||
Когда количество собранных валидных отсчетов достигает значения `smp_num`:
|
||||
|
||||
- поднимается сигнал `sample_done`
|
||||
- внутренние счетчики сбрасываются
|
||||
- буфер очищается
|
||||
- `enable` сбрасывается в `0`
|
||||
|
||||
Это означает полное завершение текущего цикла выборки.
|
||||
|
||||
---
|
||||
|
||||
## Симуляция
|
||||
Тесты запускаются автоматически через make.
|
||||
|
||||
@ -13,12 +13,17 @@ module sampler
|
||||
input rst,
|
||||
input [DATA_WIDTH-1:0] data_in,
|
||||
input out_of_range,
|
||||
input [31:0] smp_num,
|
||||
input sample_req,
|
||||
|
||||
output logic [DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata,
|
||||
output logic m_axis_tvalid
|
||||
output logic m_axis_tvalid,
|
||||
output logic sample_done
|
||||
);
|
||||
logic [DATA_WIDTH-1:0] data_converted;
|
||||
logic out_of_range_reg;
|
||||
(* MARK_DEBUG="true" *) logic [DATA_WIDTH-1:0] data_converted;
|
||||
(* MARK_DEBUG="true" *) logic out_of_range_reg;
|
||||
(* MARK_DEBUG="true" *) logic [31:0] smp_num_reg, cnt_smp_num;
|
||||
(* MARK_DEBUG="true" *) logic enable;
|
||||
|
||||
generate
|
||||
if (PROCESS_MODE) begin
|
||||
@ -50,8 +55,8 @@ module sampler
|
||||
end
|
||||
endgenerate
|
||||
|
||||
logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
|
||||
logic buffer_ready;
|
||||
(* MARK_DEBUG="true" *) logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
|
||||
(* MARK_DEBUG="true" *) logic buffer_ready;
|
||||
|
||||
logic [$clog2(PACK_FACTOR):0] cnt;
|
||||
|
||||
@ -61,12 +66,36 @@ module sampler
|
||||
if (rst) begin
|
||||
buffer <= '0;
|
||||
buffer_ready <= 0;
|
||||
cnt_smp_num <= '0;
|
||||
smp_num_reg <= '0;
|
||||
enable <= '0;
|
||||
sample_done <= 0;
|
||||
end
|
||||
else begin
|
||||
buffer_ready <= 0;
|
||||
if (!out_of_range_reg) begin
|
||||
buffer <= data_converted;
|
||||
buffer_ready <= 1;
|
||||
if (sample_done && !sample_req) begin
|
||||
sample_done <= 1'b0;
|
||||
end
|
||||
if (!enable && sample_req && !sample_done) begin
|
||||
enable <= 1;
|
||||
cnt_smp_num <= 0;
|
||||
smp_num_reg <= smp_num;
|
||||
end
|
||||
if (enable) begin
|
||||
if (!out_of_range_reg) begin
|
||||
if (cnt_smp_num != smp_num_reg) begin
|
||||
buffer <= data_converted;
|
||||
buffer_ready <= 1;
|
||||
cnt_smp_num <= cnt_smp_num +1;
|
||||
end
|
||||
else begin
|
||||
cnt_smp_num <= '0;
|
||||
sample_done <= 1'b1;
|
||||
buffer_ready <= 0;
|
||||
buffer <= '0;
|
||||
enable <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
@ -76,18 +105,42 @@ module sampler
|
||||
buffer <= '0;
|
||||
cnt <= '0; //
|
||||
buffer_ready <= 0;
|
||||
cnt_smp_num <= '0;
|
||||
smp_num_reg <= '0;
|
||||
enable <= 0;
|
||||
sample_done <= 0;
|
||||
end
|
||||
else begin
|
||||
buffer_ready <= 0;
|
||||
if (!out_of_range_reg) begin
|
||||
buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
|
||||
if (cnt == PACK_FACTOR-1) begin
|
||||
cnt <= 0;
|
||||
buffer_ready <= 1;
|
||||
buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
|
||||
end
|
||||
else begin
|
||||
cnt <= cnt + 1;
|
||||
if (sample_done && !sample_req) begin
|
||||
sample_done <= 1'b0;
|
||||
end
|
||||
if (!enable && sample_req && !sample_done) begin
|
||||
enable <= 1;
|
||||
cnt_smp_num <= 0;
|
||||
smp_num_reg <= smp_num;
|
||||
end
|
||||
if (enable) begin
|
||||
if (!out_of_range_reg) begin
|
||||
if (cnt_smp_num != smp_num_reg) begin
|
||||
cnt_smp_num <= cnt_smp_num +1;
|
||||
buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
|
||||
if (cnt == PACK_FACTOR-1) begin
|
||||
cnt <= 0;
|
||||
buffer_ready <= 1;
|
||||
buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
|
||||
end
|
||||
else begin
|
||||
cnt <= cnt + 1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
sample_done <= 1'b1;
|
||||
cnt_smp_num <= '0;
|
||||
buffer_ready <= 0;
|
||||
buffer <= '0;
|
||||
enable <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
@ -95,28 +148,6 @@ module sampler
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// always @(posedge clk_in) begin
|
||||
// if (rst) begin
|
||||
// buffer <= '0;
|
||||
// cnt <= '0; //
|
||||
// buffer_ready <= 0;
|
||||
// end
|
||||
// else begin
|
||||
// buffer_ready <= 0;
|
||||
// if (!out_of_range_reg) begin
|
||||
// buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
|
||||
// if (cnt == PACK_FACTOR-1) begin
|
||||
// cnt <= 0;
|
||||
// buffer_ready <= 1;
|
||||
// buffer <= {buffer[DATA_WIDTH*(PACK_FACTOR-1)-1:0], data_converted};
|
||||
// end
|
||||
// else begin
|
||||
// cnt <= cnt + 1;
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
|
||||
assign m_axis_tdata = buffer;
|
||||
assign m_axis_tvalid = buffer_ready;
|
||||
|
||||
|
||||
@ -1 +0,0 @@
|
||||
# mock
|
||||
@ -109,7 +109,27 @@ create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
|
||||
echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
|
||||
for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
|
||||
for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
|
||||
echo 'set ips [get_ips -quiet *]' >> $@
|
||||
echo 'if {[llength $$ips] > 0} {' >> $@
|
||||
echo ' puts "INFO: Checking IP status..."' >> $@
|
||||
echo ' report_ip_status -file ip_status_before_upgrade.rpt' >> $@
|
||||
echo ' set locked_ips [get_ips -quiet -filter {IS_LOCKED == 1}]' >> $@
|
||||
echo ' if {[llength $$locked_ips] > 0} {' >> $@
|
||||
echo ' puts "INFO: Upgrading locked IP cores: $$locked_ips"' >> $@
|
||||
echo ' upgrade_ip $$locked_ips' >> $@
|
||||
echo ' }' >> $@
|
||||
echo ' set ip_files [get_files -quiet *.xci]' >> $@
|
||||
echo ' if {[llength $$ip_files] > 0} {' >> $@
|
||||
echo ' puts "INFO: Generating IP output products..."' >> $@
|
||||
echo ' generate_target all $$ip_files' >> $@
|
||||
echo ' export_ip_user_files -of_objects $$ip_files -no_script -sync -force -quiet' >> $@
|
||||
echo ' }' >> $@
|
||||
echo ' report_ip_status -file ip_status_after_upgrade.rpt' >> $@
|
||||
echo '}' >> $@
|
||||
|
||||
for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
|
||||
|
||||
if [ -n "$(TB_FILES)" ]; then \
|
||||
echo "add_files -fileset sim_1 defines.v $(TB_FILES)" >> $@; \
|
||||
echo "set_property top $(SIM_TOP) [get_filesets sim_1]" >> $@; \
|
||||
|
||||
20
software/README.md
Normal file
20
software/README.md
Normal file
@ -0,0 +1,20 @@
|
||||
# Software
|
||||
|
||||
Просто скрипт на питоне, для отправки команд через ethernet и для приема и простой визуализации данных.
|
||||
|
||||
## Использование
|
||||
Справка:
|
||||
|
||||
```python3 --help```
|
||||
|
||||
Положительный импульс:
|
||||
|
||||
```python3 console.py --pulse_width 3500 --pulse_period 20000 --pulse_height 15000 --pulse_num 550 --dac-bits 14```
|
||||
|
||||
Отрицательный импульс:
|
||||
|
||||
```python3 console.py --pulse_width 15000 --pulse_period 20000 --pulse_height 1500 --pulse_num 550 --dac-bits 14```
|
||||
|
||||
## Ограничения
|
||||
Максимальный pulse_period считается как аппаратный N_MAX * WINDOW_SIZE * adc_dac_ratio, в базовой конфигурации это 512000. Максимальный pulse_num зависит от подаваемых значений и от битности аккумулятора (по умолчанию - 32), с учетом усреднений по WINDOW_SIZE это получается что-то около 2^14 накоплений.
|
||||
|
||||
@ -1,5 +1,9 @@
|
||||
import argparse
|
||||
import socket
|
||||
import math
|
||||
import matplotlib.pyplot as plt
|
||||
|
||||
adc_dac_ratio = 0.52
|
||||
|
||||
|
||||
def run_debug(args, sock):
|
||||
@ -22,12 +26,16 @@ def run_debug(args, sock):
|
||||
|
||||
|
||||
def format_ctrl_data(pulse_width: int, pulse_period: int,
|
||||
pulse_height: int, pulse_num: int, dac_bits: int = 16) -> bytes:
|
||||
pulse_height: int, pulse_num: int, args, dac_bits: int = 16) -> bytes:
|
||||
"""Format data packet for set_data command."""
|
||||
output = bytearray()
|
||||
|
||||
output += 0b10001000.to_bytes(1, 'little')
|
||||
|
||||
pulse_period_adc = (int(pulse_period * adc_dac_ratio) //
|
||||
args.window_size) * args.window_size
|
||||
print(pulse_period_adc)
|
||||
|
||||
# no negative please
|
||||
assert pulse_width > 0, "pulse_width should be positive"
|
||||
assert pulse_period > 0, "pulse_period should be positive"
|
||||
@ -44,8 +52,9 @@ def format_ctrl_data(pulse_width: int, pulse_period: int,
|
||||
output += pulse_period.to_bytes(4, 'little')
|
||||
output += pulse_num.to_bytes(2, 'little')
|
||||
output += pulse_height.to_bytes(2, 'little')
|
||||
output += pulse_period_adc.to_bytes(4, 'little')
|
||||
|
||||
assert len(output) == 13, "Config data should be 96 bits + 8 bit header"
|
||||
assert len(output) == 17, "Config data should be 128 bits + 8 bit header"
|
||||
return output
|
||||
|
||||
|
||||
@ -64,9 +73,53 @@ def verify_args(args):
|
||||
args.pulse_height = int(input("pulse_height: "))
|
||||
|
||||
|
||||
def recv_data(args, sock) -> list:
|
||||
# calculate count & size
|
||||
packet_count = math.ceil(
|
||||
((adc_dac_ratio * args.pulse_period) / args.window_size * args.data_width) / args.packet_size)
|
||||
print(packet_count)
|
||||
|
||||
recv_buf = []
|
||||
|
||||
try:
|
||||
for pkt_cnt in range(packet_count):
|
||||
try:
|
||||
data, address = sock.recvfrom(65536)
|
||||
|
||||
if len(data) % args.data_width != 0:
|
||||
print("invalid packet size!")
|
||||
|
||||
for i in range(0, len(data), args.data_width):
|
||||
sample = int.from_bytes(
|
||||
data[i:i+args.data_width], "little")
|
||||
recv_buf.append(sample)
|
||||
except socket.timeout:
|
||||
print("socket timeout")
|
||||
except KeyboardInterrupt:
|
||||
print(f"recv: {pkt_cnt}")
|
||||
break
|
||||
except Exception as e:
|
||||
print(f"err: {e}")
|
||||
|
||||
expected_length = math.ceil(
|
||||
adc_dac_ratio * args.pulse_period / args.window_size)
|
||||
if len(recv_buf) < expected_length:
|
||||
print("data underflow")
|
||||
return []
|
||||
|
||||
recv_buf = recv_buf[:expected_length-1]
|
||||
print(f"collected {len(recv_buf)} samples")
|
||||
# print(recv_buf)
|
||||
return recv_buf
|
||||
|
||||
|
||||
def run(args, sock):
|
||||
dest = (args.ip, args.send_port)
|
||||
|
||||
if args.pulse_period % args.window_size != 0:
|
||||
print("Invalid pulse period (should be divisable by WINDOW_SIZE)")
|
||||
return
|
||||
|
||||
# reset
|
||||
sock.sendto(0x0f00.to_bytes(2), dest)
|
||||
|
||||
@ -74,11 +127,15 @@ def run(args, sock):
|
||||
sock.sendto(format_ctrl_data(args.pulse_width,
|
||||
args.pulse_period,
|
||||
args.pulse_height,
|
||||
args.pulse_num,
|
||||
args.pulse_num, args,
|
||||
dac_bits=args.dac_bits), dest)
|
||||
|
||||
sock.sendto(0xf000.to_bytes(2), dest)
|
||||
print("Sent start!")
|
||||
data = recv_data(args, sock)
|
||||
print(min(data), max(data))
|
||||
plt.plot(data)
|
||||
plt.show()
|
||||
|
||||
|
||||
def main():
|
||||
@ -101,6 +158,15 @@ def main():
|
||||
parser.add_argument("--dac-bits", type=int, default=12,
|
||||
help="Битность ЦАП (влияет на максимальный pulse_height)")
|
||||
|
||||
parser.add_argument("--data-width", type=int,
|
||||
default=4, help="Байтность получаемых данных, по умолчанию 4 (AKA int32)")
|
||||
|
||||
parser.add_argument("--window-size", type=int,
|
||||
default=65, help="Размер окна для первого усреднения.")
|
||||
|
||||
parser.add_argument("--packet-size", type=int,
|
||||
default=1024, help="Размер отправляемых пакетов.")
|
||||
|
||||
# передача параметров через аргументы
|
||||
for arg in ("pulse_width", "pulse_period", "pulse_num", "pulse_height"):
|
||||
parser.add_argument(f"--{arg}", type=int,
|
||||
@ -109,6 +175,8 @@ def main():
|
||||
args = parser.parse_args()
|
||||
|
||||
sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
|
||||
sock.setsockopt(socket.SOL_SOCKET, socket.SO_REUSEADDR, 1)
|
||||
sock.bind(("0.0.0.0", args.recv_port))
|
||||
|
||||
if args.debug:
|
||||
run_debug(args, sock)
|
||||
|
||||
Reference in New Issue
Block a user