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dev/design #8

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baulin.fa merged 42 commits from dev/design into master 2026-05-15 16:43:19 +03:00
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+10 -9
1 changed files with 10 additions and 9 deletions
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rtl/ethernet-udp/src/eth/axis_mac.sv
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@@ -283,6 +283,8 @@ module axis_mac
reg [31:0] arp_delay;
reg arp_cached;
reg write_en_flag;
always @(posedge gmii_tx_clk or negedge rst_n) begin
if (!rst_n) begin
tx_state <= TX_IDLE;
@@ -293,8 +295,8 @@ module axis_mac
udp_send_data_length <= 16'd0;
udp_tx_req <= 1'b0;
arp_delay <= 32'b0;
write_en_flag <= 1'b0;
s_axis_tx_tready <= 1'b0;
req_ready <= 1'b0;
tx_req_len <= 16'd0;
@@ -309,8 +311,8 @@ module axis_mac
case (tx_state)
// Ready to accept a new packet request
TX_IDLE: begin
write_en_flag <= 1'b0;
udp_tx_req <= 1'b0;
s_axis_tx_tready <= 1'b0;
tx_bytes_written <= 16'd0;
tx_req_inflight <= 1'b0;
@@ -340,7 +342,6 @@ module axis_mac
// Pulse ARP request
TX_ARP_REQ: begin
req_ready <= 1'b0;
s_axis_tx_tready <= 1'b0;
udp_tx_req <= 1'b0;
arp_delay <= 32'ha000000;
@@ -350,7 +351,6 @@ module axis_mac
// Wait until ARP is resolved
TX_ARP_SEND: begin
req_ready <= 1'b0;
s_axis_tx_tready <= 1'b0;
udp_tx_req <= 1'b0;
// sent
@@ -383,7 +383,7 @@ module axis_mac
if (udp_ram_data_req) begin
udp_tx_req <= 1'b0;
s_axis_tx_tready <= 1'b1;
write_en_flag <= 1'b1;
tx_state <= TX_STREAM;
end
end
@@ -394,7 +394,6 @@ module axis_mac
udp_tx_req <= 1'b0;
// keep ready high while receiving payload bytes
s_axis_tx_tready <= (tx_bytes_written < tx_req_len);
if (s_axis_tx_tvalid && s_axis_tx_tready) begin
tx_ram_wr_data <= s_axis_tx_tdata;
@@ -403,7 +402,6 @@ module axis_mac
tx_bytes_written <= tx_bytes_written + 1'b1;
if (tx_bytes_written + 1'b1 >= tx_req_len) begin
s_axis_tx_tready <= 1'b0;
tx_state <= TX_WAIT_DRAIN;
end
end
@@ -413,7 +411,8 @@ module axis_mac
// Wait until TX RAM starts draining enough to allow
// the next request.
TX_WAIT_DRAIN: begin
s_axis_tx_tready <= 1'b0;
// s_axis_tx_tready <= 1'b0;
write_en_flag <= 1'b0;
udp_tx_req <= 1'b0;
if (udp_ram_data_count <= tx_release_threshold)
@@ -425,11 +424,13 @@ module axis_mac
tx_state <= TX_IDLE;
tx_ram_wr_en <= 1'b0;
udp_tx_req <= 1'b0;
s_axis_tx_tready <= 1'b0;
req_ready <= 1'b0;
write_en_flag <= 1'b0;
end
endcase
end
end
assign s_axis_tx_tready = write_en_flag || udp_ram_data_req;
endmodule