designs/adc_dac_synchoronizer/Makefile

@@ -7,7 +7,7 @@
 #
 
 # FPGA settings
-FPGA_PART = xc7a35tfgg484-1
+FPGA_PART = xc7a100tfgg484-2
 FPGA_TOP = sync_top
 FPGA_ARCH = artix7
 
@@ -16,13 +16,19 @@ RTL_DIR = ../../rtl
 
 include ../../scripts/vivado.mk
 
+
+SYN_FILES += $(sort $(shell find ../../rtl/sampler/src -type f -name '*.sv'))
+SYN_FILES += $(sort $(shell find ../../rtl/generator/src -type f -name '*.sv'))
 SYN_FILES += sync_top.sv
-SYN_FILES += $(sort $(shell find ../../rtl -type f \( -name '*.v' -o -name '*.sv' \)))
 
+XCI_FILES += $(sort $(shell find ip/ -type f -name '*.xci'))
 
-XDC_FILES += ../../constraints/ax7a035b.xdc
+XDC_FILES += ../../constraints/ax7102.xdc
 XDC_FILES += debug.xdc
 
+SYN_FILES += tb_sync_top.sv
+SIM_TOP = tb_top
+
 
 
 program: $(PROJECT).bit