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dev/ax7102
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dev/integr
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6
.gitmodules
vendored
Normal file
6
.gitmodules
vendored
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@ -0,0 +1,6 @@
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[submodule "libs/rtl_libs"]
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path = libs/rtl_libs
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url = https://git.radiophotonics.ru/baulin.fa/rtl_libs.git
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[submodule "libs/verilog-axi"]
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path = libs/verilog-axi
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url = https://github.com/alexforencich/verilog-axi.git
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@ -1,3 +1,10 @@
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# reflectometer_fpga_project
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# reflectometer_fpga_project
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Проект по разработке аппаратной вычислительной части для отпического рефлектометра для обнаружения утечек.
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Проект по разработке аппаратной вычислительной части для оптического рефлектометра для обнаружения утечек.
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## Структура
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- constaints: констрейны под ПЛИСы
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- designs: разные сборные дизайны, включая полный проект
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- rtl: код блоков, в каждой папке есть src и tests
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- scripts: скрипты для сборки
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- software: программные скрипты
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@ -1,5 +1,5 @@
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# Директория с тестовыми проектами под ПЛИСу
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# Директория с тестовыми проектами под ПЛИСу
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- eth_ctrl_debug: проект с ethernet и контроллером. Позволяет через ILA проверить, что пакет правильно принимается и что значения правильно выставляются.
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- adc_dac_synchronizer: проект для тестирования и отладки связки сэмплер + контроллер + генератор, проверки синхронизации между импульсами.
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- reflectometer_base: базовый проект рефлектометра без внешних интерфейсов, только I/O через AXI Stream.
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- eth_generator: проект на базе eth_ctrl_debug, в который включен генератор импульсов. В паре с ЦАП можно через консольку по Ethernet запускать генерацию разных импульсов.
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- reflectometer_prototype: тестовый проект под AX7102 с управлением и отправкой данных по ethernet.
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@ -7,7 +7,7 @@
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#
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#
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# FPGA settings
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# FPGA settings
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FPGA_PART = xc7a35tfgg484-1
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FPGA_PART = xc7a100tfgg484-2
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FPGA_TOP = sync_top
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FPGA_TOP = sync_top
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FPGA_ARCH = artix7
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FPGA_ARCH = artix7
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@ -16,13 +16,19 @@ RTL_DIR = ../../rtl
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include ../../scripts/vivado.mk
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include ../../scripts/vivado.mk
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SYN_FILES += $(sort $(shell find ../../rtl/sampler/src -type f -name '*.sv'))
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SYN_FILES += $(sort $(shell find ../../rtl/generator/src -type f -name '*.sv'))
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SYN_FILES += sync_top.sv
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SYN_FILES += sync_top.sv
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SYN_FILES += $(sort $(shell find ../../rtl -type f \( -name '*.v' -o -name '*.sv' \)))
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XCI_FILES += $(sort $(shell find ip/ -type f -name '*.xci'))
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XDC_FILES += ../../constraints/ax7a035b.xdc
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XDC_FILES += ../../constraints/ax7102.xdc
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XDC_FILES += debug.xdc
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XDC_FILES += debug.xdc
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SYN_FILES += tb_sync_top.sv
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SIM_TOP = tb_top
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program: $(PROJECT).bit
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program: $(PROJECT).bit
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@ -1,52 +0,0 @@
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# SPDX-License-Identifier: MIT
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#
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# Copyright (c) 2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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# FPGA settings
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FPGA_PART = xc7a35tfgg484-1
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FPGA_TOP = eth_ctrl_debug_top
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FPGA_ARCH = artix7
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RTL_DIR = ../../rtl
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include ../../scripts/vivado.mk
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SYN_FILES += eth_ctrl_debug.sv
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SYN_FILES += $(sort $(shell find ../../rtl -type f \( -name '*.v' -o -name '*.sv' \)))
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XCI_FILES = $(sort $(shell find ../../rtl/ethernet-udp/src -type f -name '*.xci'))
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XCI_FILES += $(sort $(shell find ip/ -type f -name '*.xci'))
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XDC_FILES += ../../constraints/ax7a035b.xdc
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XDC_FILES += debug.xdc
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program: $(PROJECT).bit
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echo "open_hw_manager" > program.tcl
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echo "connect_hw_server" >> program.tcl
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echo "open_hw_target" >> program.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
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echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
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echo "program_hw_devices [current_hw_device]" >> program.tcl
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echo "exit" >> program.tcl
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vivado -nojournal -nolog -mode batch -source program.tcl
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$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
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echo "write_cfgmem -force -format mcs -size 16 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
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echo "exit" >> generate_mcs.tcl
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vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
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mkdir -p rev
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COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.bit ]; \
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do COUNT=$$((COUNT+1)); done; \
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COUNT=$$((COUNT-1)); \
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for x in .mcs .prm; \
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do cp $*$$x rev/$*_rev$$COUNT$$x; \
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echo "Output: rev/$*_rev$$COUNT$$x"; done;
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@ -1,7 +0,0 @@
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# Тестовый проект Eth + CTRL
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Проект состоит из AXIS Ethernet и контроллера. Для тестирования сделано три разных частотных домена: ethernet 125MHz, DAC 130MHz, ADC 65MHz для тестирования сихронизации. Есть ILA на все выходы контроллера и на шину AXIS eth -> ctrl. Для отправки пакетов используйте скрипт ```console.py --debug```.
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## Сборка
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```make all``` - собрать все до битстрима
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```make vivado``` - открыть проект в Vivado
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@ -1,147 +0,0 @@
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set_clock_groups -name ASYNC_UDP_CTRL -asynchronous -group [get_clocks rgmii_rxc] -group [get_clocks clk_out1_clk_wiz_ctrl_inst] -group [get_clocks clk_out2_clk_wiz_ctrl_inst]
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create_debug_core u_ila_0 ila
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set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
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set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
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set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
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set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
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set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
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set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
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set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
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set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
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set_property port_width 1 [get_debug_ports u_ila_0/clk]
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connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out2]]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
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set_property port_width 32 [get_debug_ports u_ila_0/probe0]
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connect_debug_port u_ila_0/probe0 [get_nets [list {adc_pulse_period_dbg[0]} {adc_pulse_period_dbg[1]} {adc_pulse_period_dbg[2]} {adc_pulse_period_dbg[3]} {adc_pulse_period_dbg[4]} {adc_pulse_period_dbg[5]} {adc_pulse_period_dbg[6]} {adc_pulse_period_dbg[7]} {adc_pulse_period_dbg[8]} {adc_pulse_period_dbg[9]} {adc_pulse_period_dbg[10]} {adc_pulse_period_dbg[11]} {adc_pulse_period_dbg[12]} {adc_pulse_period_dbg[13]} {adc_pulse_period_dbg[14]} {adc_pulse_period_dbg[15]} {adc_pulse_period_dbg[16]} {adc_pulse_period_dbg[17]} {adc_pulse_period_dbg[18]} {adc_pulse_period_dbg[19]} {adc_pulse_period_dbg[20]} {adc_pulse_period_dbg[21]} {adc_pulse_period_dbg[22]} {adc_pulse_period_dbg[23]} {adc_pulse_period_dbg[24]} {adc_pulse_period_dbg[25]} {adc_pulse_period_dbg[26]} {adc_pulse_period_dbg[27]} {adc_pulse_period_dbg[28]} {adc_pulse_period_dbg[29]} {adc_pulse_period_dbg[30]} {adc_pulse_period_dbg[31]}]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
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set_property port_width 8 [get_debug_ports u_ila_0/probe1]
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connect_debug_port u_ila_0/probe1 [get_nets [list {finish_cnt[0]} {finish_cnt[1]} {finish_cnt[2]} {finish_cnt[3]} {finish_cnt[4]} {finish_cnt[5]} {finish_cnt[6]} {finish_cnt[7]}]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
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set_property port_width 16 [get_debug_ports u_ila_0/probe2]
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connect_debug_port u_ila_0/probe2 [get_nets [list {adc_pulse_num_dbg[0]} {adc_pulse_num_dbg[1]} {adc_pulse_num_dbg[2]} {adc_pulse_num_dbg[3]} {adc_pulse_num_dbg[4]} {adc_pulse_num_dbg[5]} {adc_pulse_num_dbg[6]} {adc_pulse_num_dbg[7]} {adc_pulse_num_dbg[8]} {adc_pulse_num_dbg[9]} {adc_pulse_num_dbg[10]} {adc_pulse_num_dbg[11]} {adc_pulse_num_dbg[12]} {adc_pulse_num_dbg[13]} {adc_pulse_num_dbg[14]} {adc_pulse_num_dbg[15]}]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
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set_property port_width 1 [get_debug_ports u_ila_0/probe3]
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connect_debug_port u_ila_0/probe3 [get_nets [list adc_rst_dbg]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
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set_property port_width 1 [get_debug_ports u_ila_0/probe4]
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connect_debug_port u_ila_0/probe4 [get_nets [list adc_start_dbg]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
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set_property port_width 1 [get_debug_ports u_ila_0/probe5]
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connect_debug_port u_ila_0/probe5 [get_nets [list finish_dbg]]
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create_debug_port u_ila_0 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
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set_property port_width 1 [get_debug_ports u_ila_0/probe6]
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connect_debug_port u_ila_0/probe6 [get_nets [list finish_pending]]
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create_debug_core u_ila_1 ila
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set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
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set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
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set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1]
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set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1]
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set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1]
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set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
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set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
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set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
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set_property port_width 1 [get_debug_ports u_ila_1/clk]
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connect_debug_port u_ila_1/clk [get_nets [list rgmii_rxc_IBUF_BUFG]]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
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set_property port_width 2 [get_debug_ports u_ila_1/probe0]
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connect_debug_port u_ila_1/probe0 [get_nets [list {axis_mac0/rx_state[0]} {axis_mac0/rx_state[1]}]]
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create_debug_port u_ila_1 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1]
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set_property port_width 16 [get_debug_ports u_ila_1/probe1]
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connect_debug_port u_ila_1/probe1 [get_nets [list {axis_mac0/udp_rec_data_length[0]} {axis_mac0/udp_rec_data_length[1]} {axis_mac0/udp_rec_data_length[2]} {axis_mac0/udp_rec_data_length[3]} {axis_mac0/udp_rec_data_length[4]} {axis_mac0/udp_rec_data_length[5]} {axis_mac0/udp_rec_data_length[6]} {axis_mac0/udp_rec_data_length[7]} {axis_mac0/udp_rec_data_length[8]} {axis_mac0/udp_rec_data_length[9]} {axis_mac0/udp_rec_data_length[10]} {axis_mac0/udp_rec_data_length[11]} {axis_mac0/udp_rec_data_length[12]} {axis_mac0/udp_rec_data_length[13]} {axis_mac0/udp_rec_data_length[14]} {axis_mac0/udp_rec_data_length[15]}]]
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create_debug_port u_ila_1 probe
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2]
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set_property port_width 96 [get_debug_ports u_ila_1/probe2]
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connect_debug_port u_ila_1/probe2 [get_nets [list {udp_ctrl_inst/cfg_bus_eth[0]} {udp_ctrl_inst/cfg_bus_eth[1]} {udp_ctrl_inst/cfg_bus_eth[2]} {udp_ctrl_inst/cfg_bus_eth[3]} {udp_ctrl_inst/cfg_bus_eth[4]} {udp_ctrl_inst/cfg_bus_eth[5]} {udp_ctrl_inst/cfg_bus_eth[6]} {udp_ctrl_inst/cfg_bus_eth[7]} {udp_ctrl_inst/cfg_bus_eth[8]} {udp_ctrl_inst/cfg_bus_eth[9]} {udp_ctrl_inst/cfg_bus_eth[10]} {udp_ctrl_inst/cfg_bus_eth[11]} {udp_ctrl_inst/cfg_bus_eth[12]} {udp_ctrl_inst/cfg_bus_eth[13]} {udp_ctrl_inst/cfg_bus_eth[14]} {udp_ctrl_inst/cfg_bus_eth[15]} {udp_ctrl_inst/cfg_bus_eth[16]} {udp_ctrl_inst/cfg_bus_eth[17]} {udp_ctrl_inst/cfg_bus_eth[18]} {udp_ctrl_inst/cfg_bus_eth[19]} {udp_ctrl_inst/cfg_bus_eth[20]} {udp_ctrl_inst/cfg_bus_eth[21]} {udp_ctrl_inst/cfg_bus_eth[22]} {udp_ctrl_inst/cfg_bus_eth[23]} {udp_ctrl_inst/cfg_bus_eth[24]} {udp_ctrl_inst/cfg_bus_eth[25]} {udp_ctrl_inst/cfg_bus_eth[26]} {udp_ctrl_inst/cfg_bus_eth[27]} {udp_ctrl_inst/cfg_bus_eth[28]} {udp_ctrl_inst/cfg_bus_eth[29]} {udp_ctrl_inst/cfg_bus_eth[30]} {udp_ctrl_inst/cfg_bus_eth[31]} {udp_ctrl_inst/cfg_bus_eth[32]} {udp_ctrl_inst/cfg_bus_eth[33]} {udp_ctrl_inst/cfg_bus_eth[34]} {udp_ctrl_inst/cfg_bus_eth[35]} {udp_ctrl_inst/cfg_bus_eth[36]} {udp_ctrl_inst/cfg_bus_eth[37]} {udp_ctrl_inst/cfg_bus_eth[38]} {udp_ctrl_inst/cfg_bus_eth[39]} {udp_ctrl_inst/cfg_bus_eth[40]} {udp_ctrl_inst/cfg_bus_eth[41]} {udp_ctrl_inst/cfg_bus_eth[42]} {udp_ctrl_inst/cfg_bus_eth[43]} {udp_ctrl_inst/cfg_bus_eth[44]} {udp_ctrl_inst/cfg_bus_eth[45]} {udp_ctrl_inst/cfg_bus_eth[46]} {udp_ctrl_inst/cfg_bus_eth[47]} {udp_ctrl_inst/cfg_bus_eth[48]} {udp_ctrl_inst/cfg_bus_eth[49]} {udp_ctrl_inst/cfg_bus_eth[50]} {udp_ctrl_inst/cfg_bus_eth[51]} {udp_ctrl_inst/cfg_bus_eth[52]} {udp_ctrl_inst/cfg_bus_eth[53]} {udp_ctrl_inst/cfg_bus_eth[54]} {udp_ctrl_inst/cfg_bus_eth[55]} {udp_ctrl_inst/cfg_bus_eth[56]} {udp_ctrl_inst/cfg_bus_eth[57]} {udp_ctrl_inst/cfg_bus_eth[58]} {udp_ctrl_inst/cfg_bus_eth[59]} {udp_ctrl_inst/cfg_bus_eth[60]} {udp_ctrl_inst/cfg_bus_eth[61]} {udp_ctrl_inst/cfg_bus_eth[62]} {udp_ctrl_inst/cfg_bus_eth[63]} {udp_ctrl_inst/cfg_bus_eth[64]} {udp_ctrl_inst/cfg_bus_eth[65]} {udp_ctrl_inst/cfg_bus_eth[66]} {udp_ctrl_inst/cfg_bus_eth[67]} {udp_ctrl_inst/cfg_bus_eth[68]} {udp_ctrl_inst/cfg_bus_eth[69]} {udp_ctrl_inst/cfg_bus_eth[70]} {udp_ctrl_inst/cfg_bus_eth[71]} {udp_ctrl_inst/cfg_bus_eth[72]} {udp_ctrl_inst/cfg_bus_eth[73]} {udp_ctrl_inst/cfg_bus_eth[74]} {udp_ctrl_inst/cfg_bus_eth[75]} {udp_ctrl_inst/cfg_bus_eth[76]} {udp_ctrl_inst/cfg_bus_eth[77]} {udp_ctrl_inst/cfg_bus_eth[78]} {udp_ctrl_inst/cfg_bus_eth[79]} {udp_ctrl_inst/cfg_bus_eth[80]} {udp_ctrl_inst/cfg_bus_eth[81]} {udp_ctrl_inst/cfg_bus_eth[82]} {udp_ctrl_inst/cfg_bus_eth[83]} {udp_ctrl_inst/cfg_bus_eth[84]} {udp_ctrl_inst/cfg_bus_eth[85]} {udp_ctrl_inst/cfg_bus_eth[86]} {udp_ctrl_inst/cfg_bus_eth[87]} {udp_ctrl_inst/cfg_bus_eth[88]} {udp_ctrl_inst/cfg_bus_eth[89]} {udp_ctrl_inst/cfg_bus_eth[90]} {udp_ctrl_inst/cfg_bus_eth[91]} {udp_ctrl_inst/cfg_bus_eth[92]} {udp_ctrl_inst/cfg_bus_eth[93]} {udp_ctrl_inst/cfg_bus_eth[94]} {udp_ctrl_inst/cfg_bus_eth[95]}]]
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|
||||||
create_debug_port u_ila_1 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3]
|
|
||||||
set_property port_width 16 [get_debug_ports u_ila_1/probe3]
|
|
||||||
connect_debug_port u_ila_1/probe3 [get_nets [list {axis_mac0/rx_payload_len[0]} {axis_mac0/rx_payload_len[1]} {axis_mac0/rx_payload_len[2]} {axis_mac0/rx_payload_len[3]} {axis_mac0/rx_payload_len[4]} {axis_mac0/rx_payload_len[5]} {axis_mac0/rx_payload_len[6]} {axis_mac0/rx_payload_len[7]} {axis_mac0/rx_payload_len[8]} {axis_mac0/rx_payload_len[9]} {axis_mac0/rx_payload_len[10]} {axis_mac0/rx_payload_len[11]} {axis_mac0/rx_payload_len[12]} {axis_mac0/rx_payload_len[13]} {axis_mac0/rx_payload_len[14]} {axis_mac0/rx_payload_len[15]}]]
|
|
||||||
create_debug_port u_ila_1 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4]
|
|
||||||
set_property port_width 8 [get_debug_ports u_ila_1/probe4]
|
|
||||||
connect_debug_port u_ila_1/probe4 [get_nets [list {m_axis_rx_tdata[0]} {m_axis_rx_tdata[1]} {m_axis_rx_tdata[2]} {m_axis_rx_tdata[3]} {m_axis_rx_tdata[4]} {m_axis_rx_tdata[5]} {m_axis_rx_tdata[6]} {m_axis_rx_tdata[7]}]]
|
|
||||||
create_debug_port u_ila_1 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5]
|
|
||||||
set_property port_width 3 [get_debug_ports u_ila_1/probe5]
|
|
||||||
connect_debug_port u_ila_1/probe5 [get_nets [list {udp_ctrl_inst/eth_state[0]} {udp_ctrl_inst/eth_state[1]} {udp_ctrl_inst/eth_state[2]}]]
|
|
||||||
create_debug_port u_ila_1 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_1/probe6]
|
|
||||||
connect_debug_port u_ila_1/probe6 [get_nets [list axis_mac0/arp_found]]
|
|
||||||
create_debug_port u_ila_1 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe7]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_1/probe7]
|
|
||||||
connect_debug_port u_ila_1/probe7 [get_nets [list udp_ctrl_inst/axis_hs]]
|
|
||||||
create_debug_port u_ila_1 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe8]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_1/probe8]
|
|
||||||
connect_debug_port u_ila_1/probe8 [get_nets [list udp_ctrl_inst/busy_flag_eth]]
|
|
||||||
create_debug_port u_ila_1 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe9]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_1/probe9]
|
|
||||||
connect_debug_port u_ila_1/probe9 [get_nets [list axis_mac0/m_axis_rx_tlast]]
|
|
||||||
create_debug_port u_ila_1 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe10]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_1/probe10]
|
|
||||||
connect_debug_port u_ila_1/probe10 [get_nets [list m_axis_rx_tlast]]
|
|
||||||
create_debug_port u_ila_1 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe11]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_1/probe11]
|
|
||||||
connect_debug_port u_ila_1/probe11 [get_nets [list axis_mac0/m_axis_rx_tready]]
|
|
||||||
create_debug_port u_ila_1 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe12]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_1/probe12]
|
|
||||||
connect_debug_port u_ila_1/probe12 [get_nets [list m_axis_rx_tready]]
|
|
||||||
create_debug_port u_ila_1 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe13]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_1/probe13]
|
|
||||||
connect_debug_port u_ila_1/probe13 [get_nets [list axis_mac0/req_ready]]
|
|
||||||
create_debug_core u_ila_2 ila
|
|
||||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2]
|
|
||||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2]
|
|
||||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2]
|
|
||||||
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_2]
|
|
||||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_2]
|
|
||||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2]
|
|
||||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_2]
|
|
||||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_2/clk]
|
|
||||||
connect_debug_port u_ila_2/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out1]]
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe0]
|
|
||||||
set_property port_width 12 [get_debug_ports u_ila_2/probe0]
|
|
||||||
connect_debug_port u_ila_2/probe0 [get_nets [list {dac_pulse_height_dbg[0]} {dac_pulse_height_dbg[1]} {dac_pulse_height_dbg[2]} {dac_pulse_height_dbg[3]} {dac_pulse_height_dbg[4]} {dac_pulse_height_dbg[5]} {dac_pulse_height_dbg[6]} {dac_pulse_height_dbg[7]} {dac_pulse_height_dbg[8]} {dac_pulse_height_dbg[9]} {dac_pulse_height_dbg[10]} {dac_pulse_height_dbg[11]}]]
|
|
||||||
create_debug_port u_ila_2 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe1]
|
|
||||||
set_property port_width 16 [get_debug_ports u_ila_2/probe1]
|
|
||||||
connect_debug_port u_ila_2/probe1 [get_nets [list {dac_pulse_num_dbg[0]} {dac_pulse_num_dbg[1]} {dac_pulse_num_dbg[2]} {dac_pulse_num_dbg[3]} {dac_pulse_num_dbg[4]} {dac_pulse_num_dbg[5]} {dac_pulse_num_dbg[6]} {dac_pulse_num_dbg[7]} {dac_pulse_num_dbg[8]} {dac_pulse_num_dbg[9]} {dac_pulse_num_dbg[10]} {dac_pulse_num_dbg[11]} {dac_pulse_num_dbg[12]} {dac_pulse_num_dbg[13]} {dac_pulse_num_dbg[14]} {dac_pulse_num_dbg[15]}]]
|
|
||||||
create_debug_port u_ila_2 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe2]
|
|
||||||
set_property port_width 32 [get_debug_ports u_ila_2/probe2]
|
|
||||||
connect_debug_port u_ila_2/probe2 [get_nets [list {dac_pulse_period_dbg[0]} {dac_pulse_period_dbg[1]} {dac_pulse_period_dbg[2]} {dac_pulse_period_dbg[3]} {dac_pulse_period_dbg[4]} {dac_pulse_period_dbg[5]} {dac_pulse_period_dbg[6]} {dac_pulse_period_dbg[7]} {dac_pulse_period_dbg[8]} {dac_pulse_period_dbg[9]} {dac_pulse_period_dbg[10]} {dac_pulse_period_dbg[11]} {dac_pulse_period_dbg[12]} {dac_pulse_period_dbg[13]} {dac_pulse_period_dbg[14]} {dac_pulse_period_dbg[15]} {dac_pulse_period_dbg[16]} {dac_pulse_period_dbg[17]} {dac_pulse_period_dbg[18]} {dac_pulse_period_dbg[19]} {dac_pulse_period_dbg[20]} {dac_pulse_period_dbg[21]} {dac_pulse_period_dbg[22]} {dac_pulse_period_dbg[23]} {dac_pulse_period_dbg[24]} {dac_pulse_period_dbg[25]} {dac_pulse_period_dbg[26]} {dac_pulse_period_dbg[27]} {dac_pulse_period_dbg[28]} {dac_pulse_period_dbg[29]} {dac_pulse_period_dbg[30]} {dac_pulse_period_dbg[31]}]]
|
|
||||||
create_debug_port u_ila_2 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe3]
|
|
||||||
set_property port_width 32 [get_debug_ports u_ila_2/probe3]
|
|
||||||
connect_debug_port u_ila_2/probe3 [get_nets [list {dac_pulse_width_dbg[0]} {dac_pulse_width_dbg[1]} {dac_pulse_width_dbg[2]} {dac_pulse_width_dbg[3]} {dac_pulse_width_dbg[4]} {dac_pulse_width_dbg[5]} {dac_pulse_width_dbg[6]} {dac_pulse_width_dbg[7]} {dac_pulse_width_dbg[8]} {dac_pulse_width_dbg[9]} {dac_pulse_width_dbg[10]} {dac_pulse_width_dbg[11]} {dac_pulse_width_dbg[12]} {dac_pulse_width_dbg[13]} {dac_pulse_width_dbg[14]} {dac_pulse_width_dbg[15]} {dac_pulse_width_dbg[16]} {dac_pulse_width_dbg[17]} {dac_pulse_width_dbg[18]} {dac_pulse_width_dbg[19]} {dac_pulse_width_dbg[20]} {dac_pulse_width_dbg[21]} {dac_pulse_width_dbg[22]} {dac_pulse_width_dbg[23]} {dac_pulse_width_dbg[24]} {dac_pulse_width_dbg[25]} {dac_pulse_width_dbg[26]} {dac_pulse_width_dbg[27]} {dac_pulse_width_dbg[28]} {dac_pulse_width_dbg[29]} {dac_pulse_width_dbg[30]} {dac_pulse_width_dbg[31]}]]
|
|
||||||
create_debug_port u_ila_2 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe4]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_2/probe4]
|
|
||||||
connect_debug_port u_ila_2/probe4 [get_nets [list dac_rst_dbg]]
|
|
||||||
create_debug_port u_ila_2 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe5]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_2/probe5]
|
|
||||||
connect_debug_port u_ila_2/probe5 [get_nets [list dac_start_dbg]]
|
|
||||||
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
|
|
||||||
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
|
|
||||||
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
|
|
||||||
connect_debug_port dbg_hub/clk [get_nets dac_clk]
|
|
||||||
@ -1,298 +0,0 @@
|
|||||||
`timescale 1 ns / 1 ns
|
|
||||||
|
|
||||||
module eth_ctrl_debug_top #(
|
|
||||||
parameter int unsigned DAC_DATA_WIDTH = 12
|
|
||||||
)(
|
|
||||||
input sys_clk_p,
|
|
||||||
input sys_clk_n,
|
|
||||||
input rst_n,
|
|
||||||
|
|
||||||
output [3:0] led,
|
|
||||||
|
|
||||||
output e_reset,
|
|
||||||
output e_mdc,
|
|
||||||
inout e_mdio,
|
|
||||||
|
|
||||||
output [3:0] rgmii_txd,
|
|
||||||
output rgmii_txctl,
|
|
||||||
output rgmii_txc,
|
|
||||||
input [3:0] rgmii_rxd,
|
|
||||||
input rgmii_rxctl,
|
|
||||||
input rgmii_rxc
|
|
||||||
);
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// Internal GMII-side signals
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
wire [7:0] gmii_txd;
|
|
||||||
wire gmii_tx_en;
|
|
||||||
wire gmii_tx_er;
|
|
||||||
wire gmii_tx_clk;
|
|
||||||
wire gmii_crs;
|
|
||||||
wire gmii_col;
|
|
||||||
wire [7:0] gmii_rxd_i;
|
|
||||||
wire gmii_rx_dv;
|
|
||||||
wire gmii_rx_er;
|
|
||||||
wire gmii_rx_clk;
|
|
||||||
|
|
||||||
wire [31:0] pack_total_len;
|
|
||||||
|
|
||||||
wire e_rx_dv;
|
|
||||||
wire [7:0] e_rxd;
|
|
||||||
wire e_tx_en;
|
|
||||||
wire [7:0] e_txd;
|
|
||||||
wire e_rst_n;
|
|
||||||
wire sys_clk;
|
|
||||||
|
|
||||||
wire duplex_mode;
|
|
||||||
|
|
||||||
assign duplex_mode = 1'b1;
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// System clock buffer (200 MHz differential input)
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
IBUFDS sys_clk_ibufgds (
|
|
||||||
.O (sys_clk),
|
|
||||||
.I (sys_clk_p),
|
|
||||||
.IB (sys_clk_n)
|
|
||||||
);
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// IDELAYCTRL
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
(* IODELAY_GROUP = "rgmii_idelay_group" *)
|
|
||||||
IDELAYCTRL IDELAYCTRL_inst (
|
|
||||||
.RDY (),
|
|
||||||
.REFCLK (sys_clk),
|
|
||||||
.RST (1'b0)
|
|
||||||
);
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// Generated clocks for controller
|
|
||||||
// Need to create this IP in Vivado:
|
|
||||||
// input : 200 MHz
|
|
||||||
// output0: 130 MHz
|
|
||||||
// output1: 65 MHz
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
wire dac_clk;
|
|
||||||
wire adc_clk;
|
|
||||||
wire clk_wiz_locked;
|
|
||||||
|
|
||||||
clk_wiz_ctrl_inst clk_wiz_ctrl_inst (
|
|
||||||
.clk_in1 (sys_clk),
|
|
||||||
.reset (~rst_n),
|
|
||||||
.clk_out1 (dac_clk), // 130 MHz
|
|
||||||
.clk_out2 (adc_clk), // 65 MHz
|
|
||||||
.locked (clk_wiz_locked)
|
|
||||||
);
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// GMII <-> RGMII conversion
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
util_gmii_to_rgmii util_gmii_to_rgmii_m0 (
|
|
||||||
.reset (1'b0),
|
|
||||||
.rgmii_td (rgmii_txd),
|
|
||||||
.rgmii_tx_ctl (rgmii_txctl),
|
|
||||||
.rgmii_txc (rgmii_txc),
|
|
||||||
.rgmii_rd (rgmii_rxd),
|
|
||||||
.rgmii_rx_ctl (rgmii_rxctl),
|
|
||||||
.gmii_rx_clk (gmii_rx_clk),
|
|
||||||
.gmii_txd (e_txd),
|
|
||||||
.gmii_tx_en (e_tx_en),
|
|
||||||
.gmii_tx_er (1'b0),
|
|
||||||
.gmii_tx_clk (gmii_tx_clk),
|
|
||||||
.gmii_crs (gmii_crs),
|
|
||||||
.gmii_col (gmii_col),
|
|
||||||
.gmii_rxd (gmii_rxd_i),
|
|
||||||
.rgmii_rxc (rgmii_rxc),
|
|
||||||
.gmii_rx_dv (gmii_rx_dv),
|
|
||||||
.gmii_rx_er (gmii_rx_er),
|
|
||||||
.speed_selection (2'b10),
|
|
||||||
.duplex_mode (duplex_mode)
|
|
||||||
);
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// GMII arbitration / adaptation
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
gmii_arbi arbi_inst (
|
|
||||||
.clk (gmii_tx_clk),
|
|
||||||
.rst_n (rst_n),
|
|
||||||
.speed (2'b10),
|
|
||||||
.link (1'b1),
|
|
||||||
.pack_total_len (pack_total_len),
|
|
||||||
.e_rst_n (e_rst_n),
|
|
||||||
.gmii_rx_dv (gmii_rx_dv),
|
|
||||||
.gmii_rxd (gmii_rxd_i),
|
|
||||||
.gmii_tx_en (gmii_tx_en),
|
|
||||||
.gmii_txd (gmii_txd),
|
|
||||||
.e_rx_dv (e_rx_dv),
|
|
||||||
.e_rxd (e_rxd),
|
|
||||||
.e_tx_en (e_tx_en),
|
|
||||||
.e_txd (e_txd)
|
|
||||||
);
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// axis_mac interface
|
|
||||||
// RX stream from Ethernet goes into controller
|
|
||||||
// TX stream is unused for now
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
wire req_ready;
|
|
||||||
|
|
||||||
reg send_req;
|
|
||||||
reg [15:0] data_length;
|
|
||||||
|
|
||||||
reg [7:0] s_axis_tx_tdata;
|
|
||||||
reg s_axis_tx_tvalid;
|
|
||||||
wire s_axis_tx_tready;
|
|
||||||
reg s_axis_tx_tlast;
|
|
||||||
|
|
||||||
(* MARK_DEBUG="true" *) wire [7:0] m_axis_rx_tdata;
|
|
||||||
(* MARK_DEBUG="true" *) wire m_axis_rx_tvalid;
|
|
||||||
(* MARK_DEBUG="true" *) wire m_axis_rx_tlast;
|
|
||||||
(* MARK_DEBUG="true" *) wire m_axis_rx_tready;
|
|
||||||
|
|
||||||
// Always ready to accept RX payload bytes
|
|
||||||
assign m_axis_rx_tready = 1'b1;
|
|
||||||
|
|
||||||
// TX disabled
|
|
||||||
always @(*) begin
|
|
||||||
send_req = 1'b0;
|
|
||||||
data_length = 16'd0;
|
|
||||||
s_axis_tx_tdata = 8'd0;
|
|
||||||
s_axis_tx_tvalid= 1'b0;
|
|
||||||
s_axis_tx_tlast = 1'b0;
|
|
||||||
end
|
|
||||||
|
|
||||||
axis_mac axis_mac0 (
|
|
||||||
.gmii_tx_clk (gmii_tx_clk),
|
|
||||||
.gmii_rx_clk (gmii_rx_clk),
|
|
||||||
.rst_n (e_rst_n),
|
|
||||||
|
|
||||||
.gmii_rx_dv (e_rx_dv),
|
|
||||||
.gmii_rxd (e_rxd),
|
|
||||||
.gmii_tx_en (gmii_tx_en),
|
|
||||||
.gmii_txd (gmii_txd),
|
|
||||||
|
|
||||||
.send_req (send_req),
|
|
||||||
.data_length (data_length),
|
|
||||||
.req_ready (req_ready),
|
|
||||||
|
|
||||||
.s_axis_tx_tdata (s_axis_tx_tdata),
|
|
||||||
.s_axis_tx_tvalid (s_axis_tx_tvalid),
|
|
||||||
.s_axis_tx_tready (s_axis_tx_tready),
|
|
||||||
.s_axis_tx_tlast (s_axis_tx_tlast),
|
|
||||||
|
|
||||||
.m_axis_rx_tdata (m_axis_rx_tdata),
|
|
||||||
.m_axis_rx_tvalid (m_axis_rx_tvalid),
|
|
||||||
.m_axis_rx_tready (m_axis_rx_tready),
|
|
||||||
.m_axis_rx_tlast (m_axis_rx_tlast)
|
|
||||||
);
|
|
||||||
|
|
||||||
// PHY reset helper from your original example
|
|
||||||
reset reset_m0 (
|
|
||||||
.clk (sys_clk),
|
|
||||||
.key1 (rst_n),
|
|
||||||
.rst_n (e_reset)
|
|
||||||
);
|
|
||||||
|
|
||||||
// MDIO lines are not driven here yet
|
|
||||||
assign e_mdc = 1'b0;
|
|
||||||
assign e_mdio = 1'bz;
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// Controller reset
|
|
||||||
// Use both external reset and clk_wiz lock
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
wire ctrl_rst_n = rst_n & clk_wiz_locked;
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// Debug finish generator
|
|
||||||
//
|
|
||||||
// After each adc_start pulse generates one finish pulse after some delay.
|
|
||||||
// This is just for first bring-up so the controller can leave busy state
|
|
||||||
// If you don't want this, replace with:
|
|
||||||
// wire finish_dbg = 1'b0;
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
(* MARK_DEBUG="true" *) logic finish_dbg;
|
|
||||||
(* MARK_DEBUG="true" *) logic [7:0] finish_cnt;
|
|
||||||
(* MARK_DEBUG="true" *) logic finish_pending;
|
|
||||||
|
|
||||||
// Controller outputs to debug
|
|
||||||
(* MARK_DEBUG="true" *) wire [31:0] dac_pulse_width_dbg;
|
|
||||||
(* MARK_DEBUG="true" *) wire [31:0] dac_pulse_period_dbg;
|
|
||||||
(* MARK_DEBUG="true" *) wire [DAC_DATA_WIDTH-1:0] dac_pulse_height_dbg;
|
|
||||||
(* MARK_DEBUG="true" *) wire [15:0] dac_pulse_num_dbg;
|
|
||||||
|
|
||||||
(* MARK_DEBUG="true" *) wire [31:0] adc_pulse_period_dbg;
|
|
||||||
(* MARK_DEBUG="true" *) wire [15:0] adc_pulse_num_dbg;
|
|
||||||
|
|
||||||
(* MARK_DEBUG="true" *) wire dac_start_dbg;
|
|
||||||
(* MARK_DEBUG="true" *) wire adc_start_dbg;
|
|
||||||
(* MARK_DEBUG="true" *) wire dac_rst_dbg;
|
|
||||||
(* MARK_DEBUG="true" *) wire adc_rst_dbg;
|
|
||||||
|
|
||||||
always_ff @(posedge adc_clk or negedge ctrl_rst_n) begin
|
|
||||||
if (!ctrl_rst_n) begin
|
|
||||||
finish_dbg <= 1'b0;
|
|
||||||
finish_cnt <= 8'd0;
|
|
||||||
finish_pending <= 1'b0;
|
|
||||||
end else begin
|
|
||||||
finish_dbg <= 1'b0;
|
|
||||||
|
|
||||||
if (adc_start_dbg) begin
|
|
||||||
finish_pending <= 1'b1;
|
|
||||||
finish_cnt <= 8'd80;
|
|
||||||
end else if (finish_pending) begin
|
|
||||||
if (finish_cnt == 8'd0) begin
|
|
||||||
finish_dbg <= 1'b1;
|
|
||||||
finish_pending <= 1'b0;
|
|
||||||
end else begin
|
|
||||||
finish_cnt <= finish_cnt - 8'd1;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// Controller
|
|
||||||
// ETH domain = gmii_rx_clk, because RX AXI master comes from axis_mac RX side
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
control #(
|
|
||||||
.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
|
|
||||||
) udp_ctrl_inst (
|
|
||||||
.eth_clk_in (gmii_rx_clk),
|
|
||||||
.dac_clk_in (dac_clk),
|
|
||||||
.adc_clk_in (adc_clk),
|
|
||||||
.rst_n (ctrl_rst_n),
|
|
||||||
|
|
||||||
.s_axis_tdata (m_axis_rx_tdata),
|
|
||||||
.s_axis_tvalid (m_axis_rx_tvalid),
|
|
||||||
.s_axis_tready (), // controller internally always ready in current version
|
|
||||||
.s_axis_tlast (m_axis_rx_tlast),
|
|
||||||
|
|
||||||
.finish (finish_dbg),
|
|
||||||
|
|
||||||
.dac_pulse_width (dac_pulse_width_dbg),
|
|
||||||
.dac_pulse_period (dac_pulse_period_dbg),
|
|
||||||
.dac_pulse_height (dac_pulse_height_dbg),
|
|
||||||
.dac_pulse_num (dac_pulse_num_dbg),
|
|
||||||
|
|
||||||
.adc_pulse_period (adc_pulse_period_dbg),
|
|
||||||
.adc_pulse_num (adc_pulse_num_dbg),
|
|
||||||
|
|
||||||
.dac_start (dac_start_dbg),
|
|
||||||
.adc_start (adc_start_dbg),
|
|
||||||
|
|
||||||
.dac_rst (dac_rst_dbg),
|
|
||||||
.adc_rst (adc_rst_dbg)
|
|
||||||
);
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// Simple LED status
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
assign led[0] = clk_wiz_locked;
|
|
||||||
assign led[1] = m_axis_rx_tvalid;
|
|
||||||
assign led[2] = dac_start_dbg;
|
|
||||||
assign led[3] = adc_rst_dbg;
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
@ -1,689 +0,0 @@
|
|||||||
{
|
|
||||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
|
||||||
"ip_inst": {
|
|
||||||
"xci_name": "clk_wiz_ctrl_inst",
|
|
||||||
"component_reference": "xilinx.com:ip:clk_wiz:6.0",
|
|
||||||
"ip_revision": "16",
|
|
||||||
"gen_directory": "../../../../eth_ctrl_debug_top.gen/sources_1/ip/clk_wiz_ctrl_inst",
|
|
||||||
"parameters": {
|
|
||||||
"component_parameters": {
|
|
||||||
"Component_Name": [ { "value": "clk_wiz_ctrl_inst", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PRIM_IN_FREQ": [ { "value": "200.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKIN1_JITTER_PS": [ { "value": "50.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"NUM_OUT_CLKS": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "130.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "65.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"USE_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"MMCM_DIVCLK_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"MMCM_CLKFBOUT_MULT_F": [ { "value": "4.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT0_DIVIDE_F": [ { "value": "7.500", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT1_DIVIDE": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT1_JITTER": [ { "value": "102.676", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT1_PHASE_ERROR": [ { "value": "87.159", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT2_JITTER": [ { "value": "117.878", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT2_PHASE_ERROR": [ { "value": "87.159", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT4_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT4_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
|
||||||
},
|
|
||||||
"model_parameters": {
|
|
||||||
"C_CLKOUT2_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"c_component_name": [ { "value": "clk_wiz_ctrl_inst", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_PHASE_ALIGNMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PRIM_IN_FREQ": [ { "value": "200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_USE_RESET": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_NUM_OUT_CLKS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_INCLK_SUM_ROW0": [ { "value": "Input Clock Freq (MHz) Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_INCLK_SUM_ROW1": [ { "value": "__primary_________200.000____________0.010", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__130.00000______0.000______50.0______102.676_____87.159", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__65.00000______0.000______50.0______117.878_____87.159", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "130.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "65.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_OUT_FREQ": [ { "value": "130.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_OUT_FREQ": [ { "value": "65.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKFBOUT_MULT_F": [ { "value": "4.875", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
|
||||||
"C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "7.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT1_DIVIDE": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKIN1_JITTER_PS": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIVIDE2_AUTO": [ { "value": "2.0", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIVIDE3_AUTO": [ { "value": "0.13333333333333333", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIVIDE4_AUTO": [ { "value": "0.13333333333333333", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIVIDE5_AUTO": [ { "value": "0.13333333333333333", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIVIDE6_AUTO": [ { "value": "0.13333333333333333", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIVIDE7_AUTO": [ { "value": "0.13333333333333333", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT0_ACTUAL_FREQ": [ { "value": "130.00000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_ACTUAL_FREQ": [ { "value": "65.00000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_D_MAX": [ { "value": "80.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_VCO_MIN": [ { "value": "600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_VCO_MAX": [ { "value": "1200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
|
|
||||||
},
|
|
||||||
"project_parameters": {
|
|
||||||
"ARCHITECTURE": [ { "value": "artix7" } ],
|
|
||||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
|
||||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
|
||||||
"DEVICE": [ { "value": "xc7a35t" } ],
|
|
||||||
"PACKAGE": [ { "value": "fgg484" } ],
|
|
||||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
|
||||||
"SILICON_REVISION": [ { "value": "" } ],
|
|
||||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
|
||||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
|
||||||
"STATIC_POWER": [ { "value": "" } ],
|
|
||||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
|
||||||
},
|
|
||||||
"runtime_parameters": {
|
|
||||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
|
||||||
"IPREVISION": [ { "value": "16" } ],
|
|
||||||
"MANAGED": [ { "value": "TRUE" } ],
|
|
||||||
"OUTPUTDIR": [ { "value": "../../../../eth_ctrl_debug_top.gen/sources_1/ip/clk_wiz_ctrl_inst" } ],
|
|
||||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
|
||||||
"SHAREDDIR": [ { "value": "." } ],
|
|
||||||
"SWVERSION": [ { "value": "2025.1" } ],
|
|
||||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"boundary": {
|
|
||||||
"ports": {
|
|
||||||
"reset": [ { "direction": "in", "driver_value": "0" } ],
|
|
||||||
"clk_in1": [ { "direction": "in" } ],
|
|
||||||
"clk_out1": [ { "direction": "out" } ],
|
|
||||||
"clk_out2": [ { "direction": "out" } ],
|
|
||||||
"locked": [ { "direction": "out" } ]
|
|
||||||
},
|
|
||||||
"interfaces": {
|
|
||||||
"reset": {
|
|
||||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
|
||||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
|
||||||
"mode": "slave",
|
|
||||||
"parameters": {
|
|
||||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
|
|
||||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "usage": "all" } ],
|
|
||||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
|
||||||
},
|
|
||||||
"port_maps": {
|
|
||||||
"RST": [ { "physical_name": "reset" } ]
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"clock_CLK_IN1": {
|
|
||||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
|
||||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
|
||||||
"mode": "slave",
|
|
||||||
"parameters": {
|
|
||||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ]
|
|
||||||
},
|
|
||||||
"port_maps": {
|
|
||||||
"CLK_IN1": [ { "physical_name": "clk_in1" } ]
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"clock_CLK_OUT1": {
|
|
||||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
|
||||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
|
||||||
"mode": "master",
|
|
||||||
"parameters": {
|
|
||||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
|
||||||
},
|
|
||||||
"port_maps": {
|
|
||||||
"CLK_OUT1": [ { "physical_name": "clk_out1" } ]
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"clock_CLK_OUT2": {
|
|
||||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
|
||||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
|
||||||
"mode": "master",
|
|
||||||
"parameters": {
|
|
||||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
|
||||||
},
|
|
||||||
"port_maps": {
|
|
||||||
"CLK_OUT2": [ { "physical_name": "clk_out2" } ]
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
@ -1,52 +0,0 @@
|
|||||||
# SPDX-License-Identifier: MIT
|
|
||||||
#
|
|
||||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
|
||||||
#
|
|
||||||
# Authors:
|
|
||||||
# - Alex Forencich
|
|
||||||
#
|
|
||||||
|
|
||||||
# FPGA settings
|
|
||||||
FPGA_PART = xc7a35tfgg484-1
|
|
||||||
FPGA_TOP = eth_generator_top
|
|
||||||
FPGA_ARCH = artix7
|
|
||||||
|
|
||||||
RTL_DIR = ../../rtl
|
|
||||||
|
|
||||||
|
|
||||||
include ../../scripts/vivado.mk
|
|
||||||
|
|
||||||
SYN_FILES += eth_generator.sv
|
|
||||||
SYN_FILES += $(sort $(shell find ../../rtl -type f \( -name '*.v' -o -name '*.sv' \)))
|
|
||||||
|
|
||||||
XCI_FILES = $(sort $(shell find ../../rtl/ethernet-udp/src -type f -name '*.xci'))
|
|
||||||
XCI_FILES += $(sort $(shell find ip/ -type f -name '*.xci'))
|
|
||||||
|
|
||||||
XDC_FILES += ../../constraints/ax7a035b.xdc
|
|
||||||
XDC_FILES += debug.xdc
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
program: $(PROJECT).bit
|
|
||||||
echo "open_hw_manager" > program.tcl
|
|
||||||
echo "connect_hw_server" >> program.tcl
|
|
||||||
echo "open_hw_target" >> program.tcl
|
|
||||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
|
||||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
|
||||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
|
||||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
|
||||||
echo "exit" >> program.tcl
|
|
||||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
|
||||||
|
|
||||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
|
||||||
echo "write_cfgmem -force -format mcs -size 16 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
|
||||||
echo "exit" >> generate_mcs.tcl
|
|
||||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
|
||||||
mkdir -p rev
|
|
||||||
COUNT=100; \
|
|
||||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
|
||||||
do COUNT=$$((COUNT+1)); done; \
|
|
||||||
COUNT=$$((COUNT-1)); \
|
|
||||||
for x in .mcs .prm; \
|
|
||||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
|
||||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
|
||||||
@ -1,11 +0,0 @@
|
|||||||
# Тестовый проект Generator + ETH + CTRL
|
|
||||||
Проект состоит из AXIS Ethernet, контроллера и генератора. Позволяет генерировать сигналы, задав параметры через Ethernet.
|
|
||||||
## Сборка
|
|
||||||
```make all``` - собрать все до битстрима
|
|
||||||
|
|
||||||
```make vivado``` - открыть проект в Vivado
|
|
||||||
|
|
||||||
## Управление
|
|
||||||
Используйте software/console.py. Пример:
|
|
||||||
|
|
||||||
```python3 console.py --pulse_width 3_500_000 --pulse_period 20_000_000 --pulse_height 10000 --pulse_num 5500 --dac-bits 14```
|
|
||||||
@ -1,117 +0,0 @@
|
|||||||
set_clock_groups -name ASYNC_UDP_CTRL -asynchronous -group [get_clocks rgmii_rxc] -group [get_clocks clk_out1_clk_wiz_ctrl_inst] -group [get_clocks clk_out2_clk_wiz_ctrl_inst]
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
connect_debug_port u_ila_2/probe0 [get_nets [list {dac_pulse_height_dbg[0]} {dac_pulse_height_dbg[1]} {dac_pulse_height_dbg[2]} {dac_pulse_height_dbg[3]} {dac_pulse_height_dbg[4]} {dac_pulse_height_dbg[5]} {dac_pulse_height_dbg[6]} {dac_pulse_height_dbg[7]} {dac_pulse_height_dbg[8]} {dac_pulse_height_dbg[9]} {dac_pulse_height_dbg[10]} {dac_pulse_height_dbg[11]}]]
|
|
||||||
connect_debug_port u_ila_2/probe1 [get_nets [list {dac_pulse_num_dbg[0]} {dac_pulse_num_dbg[1]} {dac_pulse_num_dbg[2]} {dac_pulse_num_dbg[3]} {dac_pulse_num_dbg[4]} {dac_pulse_num_dbg[5]} {dac_pulse_num_dbg[6]} {dac_pulse_num_dbg[7]} {dac_pulse_num_dbg[8]} {dac_pulse_num_dbg[9]} {dac_pulse_num_dbg[10]} {dac_pulse_num_dbg[11]} {dac_pulse_num_dbg[12]} {dac_pulse_num_dbg[13]} {dac_pulse_num_dbg[14]} {dac_pulse_num_dbg[15]}]]
|
|
||||||
connect_debug_port u_ila_2/probe2 [get_nets [list {dac_pulse_period_dbg[0]} {dac_pulse_period_dbg[1]} {dac_pulse_period_dbg[2]} {dac_pulse_period_dbg[3]} {dac_pulse_period_dbg[4]} {dac_pulse_period_dbg[5]} {dac_pulse_period_dbg[6]} {dac_pulse_period_dbg[7]} {dac_pulse_period_dbg[8]} {dac_pulse_period_dbg[9]} {dac_pulse_period_dbg[10]} {dac_pulse_period_dbg[11]} {dac_pulse_period_dbg[12]} {dac_pulse_period_dbg[13]} {dac_pulse_period_dbg[14]} {dac_pulse_period_dbg[15]} {dac_pulse_period_dbg[16]} {dac_pulse_period_dbg[17]} {dac_pulse_period_dbg[18]} {dac_pulse_period_dbg[19]} {dac_pulse_period_dbg[20]} {dac_pulse_period_dbg[21]} {dac_pulse_period_dbg[22]} {dac_pulse_period_dbg[23]} {dac_pulse_period_dbg[24]} {dac_pulse_period_dbg[25]} {dac_pulse_period_dbg[26]} {dac_pulse_period_dbg[27]} {dac_pulse_period_dbg[28]} {dac_pulse_period_dbg[29]} {dac_pulse_period_dbg[30]} {dac_pulse_period_dbg[31]}]]
|
|
||||||
connect_debug_port u_ila_2/probe3 [get_nets [list {dac_pulse_width_dbg[0]} {dac_pulse_width_dbg[1]} {dac_pulse_width_dbg[2]} {dac_pulse_width_dbg[3]} {dac_pulse_width_dbg[4]} {dac_pulse_width_dbg[5]} {dac_pulse_width_dbg[6]} {dac_pulse_width_dbg[7]} {dac_pulse_width_dbg[8]} {dac_pulse_width_dbg[9]} {dac_pulse_width_dbg[10]} {dac_pulse_width_dbg[11]} {dac_pulse_width_dbg[12]} {dac_pulse_width_dbg[13]} {dac_pulse_width_dbg[14]} {dac_pulse_width_dbg[15]} {dac_pulse_width_dbg[16]} {dac_pulse_width_dbg[17]} {dac_pulse_width_dbg[18]} {dac_pulse_width_dbg[19]} {dac_pulse_width_dbg[20]} {dac_pulse_width_dbg[21]} {dac_pulse_width_dbg[22]} {dac_pulse_width_dbg[23]} {dac_pulse_width_dbg[24]} {dac_pulse_width_dbg[25]} {dac_pulse_width_dbg[26]} {dac_pulse_width_dbg[27]} {dac_pulse_width_dbg[28]} {dac_pulse_width_dbg[29]} {dac_pulse_width_dbg[30]} {dac_pulse_width_dbg[31]}]]
|
|
||||||
connect_debug_port u_ila_2/probe4 [get_nets [list dac_rst_dbg]]
|
|
||||||
connect_debug_port u_ila_2/probe5 [get_nets [list dac_start_dbg]]
|
|
||||||
|
|
||||||
|
|
||||||
connect_debug_port u_ila_1/probe7 [get_nets [list p2_wrt_OBUF]]
|
|
||||||
|
|
||||||
create_debug_core u_ila_0 ila
|
|
||||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
|
||||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
|
|
||||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
|
|
||||||
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
|
|
||||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
|
|
||||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
|
||||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
|
||||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_0/clk]
|
|
||||||
connect_debug_port u_ila_0/clk [get_nets [list rgmii_rxc_IBUF_BUFG]]
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
|
||||||
set_property port_width 3 [get_debug_ports u_ila_0/probe0]
|
|
||||||
connect_debug_port u_ila_0/probe0 [get_nets [list {udp_ctrl_inst/eth_state[0]} {udp_ctrl_inst/eth_state[1]} {udp_ctrl_inst/eth_state[2]}]]
|
|
||||||
create_debug_port u_ila_0 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
|
||||||
set_property port_width 96 [get_debug_ports u_ila_0/probe1]
|
|
||||||
connect_debug_port u_ila_0/probe1 [get_nets [list {udp_ctrl_inst/cfg_bus_eth[0]} {udp_ctrl_inst/cfg_bus_eth[1]} {udp_ctrl_inst/cfg_bus_eth[2]} {udp_ctrl_inst/cfg_bus_eth[3]} {udp_ctrl_inst/cfg_bus_eth[4]} {udp_ctrl_inst/cfg_bus_eth[5]} {udp_ctrl_inst/cfg_bus_eth[6]} {udp_ctrl_inst/cfg_bus_eth[7]} {udp_ctrl_inst/cfg_bus_eth[8]} {udp_ctrl_inst/cfg_bus_eth[9]} {udp_ctrl_inst/cfg_bus_eth[10]} {udp_ctrl_inst/cfg_bus_eth[11]} {udp_ctrl_inst/cfg_bus_eth[12]} {udp_ctrl_inst/cfg_bus_eth[13]} {udp_ctrl_inst/cfg_bus_eth[14]} {udp_ctrl_inst/cfg_bus_eth[15]} {udp_ctrl_inst/cfg_bus_eth[16]} {udp_ctrl_inst/cfg_bus_eth[17]} {udp_ctrl_inst/cfg_bus_eth[18]} {udp_ctrl_inst/cfg_bus_eth[19]} {udp_ctrl_inst/cfg_bus_eth[20]} {udp_ctrl_inst/cfg_bus_eth[21]} {udp_ctrl_inst/cfg_bus_eth[22]} {udp_ctrl_inst/cfg_bus_eth[23]} {udp_ctrl_inst/cfg_bus_eth[24]} {udp_ctrl_inst/cfg_bus_eth[25]} {udp_ctrl_inst/cfg_bus_eth[26]} {udp_ctrl_inst/cfg_bus_eth[27]} {udp_ctrl_inst/cfg_bus_eth[28]} {udp_ctrl_inst/cfg_bus_eth[29]} {udp_ctrl_inst/cfg_bus_eth[30]} {udp_ctrl_inst/cfg_bus_eth[31]} {udp_ctrl_inst/cfg_bus_eth[32]} {udp_ctrl_inst/cfg_bus_eth[33]} {udp_ctrl_inst/cfg_bus_eth[34]} {udp_ctrl_inst/cfg_bus_eth[35]} {udp_ctrl_inst/cfg_bus_eth[36]} {udp_ctrl_inst/cfg_bus_eth[37]} {udp_ctrl_inst/cfg_bus_eth[38]} {udp_ctrl_inst/cfg_bus_eth[39]} {udp_ctrl_inst/cfg_bus_eth[40]} {udp_ctrl_inst/cfg_bus_eth[41]} {udp_ctrl_inst/cfg_bus_eth[42]} {udp_ctrl_inst/cfg_bus_eth[43]} {udp_ctrl_inst/cfg_bus_eth[44]} {udp_ctrl_inst/cfg_bus_eth[45]} {udp_ctrl_inst/cfg_bus_eth[46]} {udp_ctrl_inst/cfg_bus_eth[47]} {udp_ctrl_inst/cfg_bus_eth[48]} {udp_ctrl_inst/cfg_bus_eth[49]} {udp_ctrl_inst/cfg_bus_eth[50]} {udp_ctrl_inst/cfg_bus_eth[51]} {udp_ctrl_inst/cfg_bus_eth[52]} {udp_ctrl_inst/cfg_bus_eth[53]} {udp_ctrl_inst/cfg_bus_eth[54]} {udp_ctrl_inst/cfg_bus_eth[55]} {udp_ctrl_inst/cfg_bus_eth[56]} {udp_ctrl_inst/cfg_bus_eth[57]} {udp_ctrl_inst/cfg_bus_eth[58]} {udp_ctrl_inst/cfg_bus_eth[59]} {udp_ctrl_inst/cfg_bus_eth[60]} {udp_ctrl_inst/cfg_bus_eth[61]} {udp_ctrl_inst/cfg_bus_eth[62]} {udp_ctrl_inst/cfg_bus_eth[63]} {udp_ctrl_inst/cfg_bus_eth[64]} {udp_ctrl_inst/cfg_bus_eth[65]} {udp_ctrl_inst/cfg_bus_eth[66]} {udp_ctrl_inst/cfg_bus_eth[67]} {udp_ctrl_inst/cfg_bus_eth[68]} {udp_ctrl_inst/cfg_bus_eth[69]} {udp_ctrl_inst/cfg_bus_eth[70]} {udp_ctrl_inst/cfg_bus_eth[71]} {udp_ctrl_inst/cfg_bus_eth[72]} {udp_ctrl_inst/cfg_bus_eth[73]} {udp_ctrl_inst/cfg_bus_eth[74]} {udp_ctrl_inst/cfg_bus_eth[75]} {udp_ctrl_inst/cfg_bus_eth[76]} {udp_ctrl_inst/cfg_bus_eth[77]} {udp_ctrl_inst/cfg_bus_eth[78]} {udp_ctrl_inst/cfg_bus_eth[79]} {udp_ctrl_inst/cfg_bus_eth[80]} {udp_ctrl_inst/cfg_bus_eth[81]} {udp_ctrl_inst/cfg_bus_eth[82]} {udp_ctrl_inst/cfg_bus_eth[83]} {udp_ctrl_inst/cfg_bus_eth[84]} {udp_ctrl_inst/cfg_bus_eth[85]} {udp_ctrl_inst/cfg_bus_eth[86]} {udp_ctrl_inst/cfg_bus_eth[87]} {udp_ctrl_inst/cfg_bus_eth[88]} {udp_ctrl_inst/cfg_bus_eth[89]} {udp_ctrl_inst/cfg_bus_eth[90]} {udp_ctrl_inst/cfg_bus_eth[91]} {udp_ctrl_inst/cfg_bus_eth[92]} {udp_ctrl_inst/cfg_bus_eth[93]} {udp_ctrl_inst/cfg_bus_eth[94]} {udp_ctrl_inst/cfg_bus_eth[95]}]]
|
|
||||||
create_debug_port u_ila_0 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
|
||||||
set_property port_width 8 [get_debug_ports u_ila_0/probe2]
|
|
||||||
connect_debug_port u_ila_0/probe2 [get_nets [list {m_axis_rx_tdata[0]} {m_axis_rx_tdata[1]} {m_axis_rx_tdata[2]} {m_axis_rx_tdata[3]} {m_axis_rx_tdata[4]} {m_axis_rx_tdata[5]} {m_axis_rx_tdata[6]} {m_axis_rx_tdata[7]}]]
|
|
||||||
create_debug_port u_ila_0 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_0/probe3]
|
|
||||||
connect_debug_port u_ila_0/probe3 [get_nets [list udp_ctrl_inst/axis_hs]]
|
|
||||||
create_debug_port u_ila_0 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
|
|
||||||
connect_debug_port u_ila_0/probe4 [get_nets [list udp_ctrl_inst/busy_flag_eth]]
|
|
||||||
create_debug_port u_ila_0 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
|
|
||||||
connect_debug_port u_ila_0/probe5 [get_nets [list m_axis_rx_tlast]]
|
|
||||||
create_debug_port u_ila_0 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
|
|
||||||
connect_debug_port u_ila_0/probe6 [get_nets [list m_axis_rx_tready]]
|
|
||||||
create_debug_core u_ila_1 ila
|
|
||||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
|
|
||||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
|
|
||||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1]
|
|
||||||
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1]
|
|
||||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1]
|
|
||||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
|
|
||||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
|
|
||||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_1/clk]
|
|
||||||
connect_debug_port u_ila_1/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out1]]
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
|
|
||||||
set_property port_width 14 [get_debug_ports u_ila_1/probe0]
|
|
||||||
connect_debug_port u_ila_1/probe0 [get_nets [list {p2_data_OBUF[0]} {p2_data_OBUF[1]} {p2_data_OBUF[2]} {p2_data_OBUF[3]} {p2_data_OBUF[4]} {p2_data_OBUF[5]} {p2_data_OBUF[6]} {p2_data_OBUF[7]} {p2_data_OBUF[8]} {p2_data_OBUF[9]} {p2_data_OBUF[10]} {p2_data_OBUF[11]} {p2_data_OBUF[12]} {p2_data_OBUF[13]}]]
|
|
||||||
create_debug_port u_ila_1 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe1]
|
|
||||||
set_property port_width 16 [get_debug_ports u_ila_1/probe1]
|
|
||||||
connect_debug_port u_ila_1/probe1 [get_nets [list {dac_pulse_num[0]} {dac_pulse_num[1]} {dac_pulse_num[2]} {dac_pulse_num[3]} {dac_pulse_num[4]} {dac_pulse_num[5]} {dac_pulse_num[6]} {dac_pulse_num[7]} {dac_pulse_num[8]} {dac_pulse_num[9]} {dac_pulse_num[10]} {dac_pulse_num[11]} {dac_pulse_num[12]} {dac_pulse_num[13]} {dac_pulse_num[14]} {dac_pulse_num[15]}]]
|
|
||||||
create_debug_port u_ila_1 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe2]
|
|
||||||
set_property port_width 14 [get_debug_ports u_ila_1/probe2]
|
|
||||||
connect_debug_port u_ila_1/probe2 [get_nets [list {dac_pulse_height[0]} {dac_pulse_height[1]} {dac_pulse_height[2]} {dac_pulse_height[3]} {dac_pulse_height[4]} {dac_pulse_height[5]} {dac_pulse_height[6]} {dac_pulse_height[7]} {dac_pulse_height[8]} {dac_pulse_height[9]} {dac_pulse_height[10]} {dac_pulse_height[11]} {dac_pulse_height[12]} {dac_pulse_height[13]}]]
|
|
||||||
create_debug_port u_ila_1 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe3]
|
|
||||||
set_property port_width 32 [get_debug_ports u_ila_1/probe3]
|
|
||||||
connect_debug_port u_ila_1/probe3 [get_nets [list {dac_pulse_period[0]} {dac_pulse_period[1]} {dac_pulse_period[2]} {dac_pulse_period[3]} {dac_pulse_period[4]} {dac_pulse_period[5]} {dac_pulse_period[6]} {dac_pulse_period[7]} {dac_pulse_period[8]} {dac_pulse_period[9]} {dac_pulse_period[10]} {dac_pulse_period[11]} {dac_pulse_period[12]} {dac_pulse_period[13]} {dac_pulse_period[14]} {dac_pulse_period[15]} {dac_pulse_period[16]} {dac_pulse_period[17]} {dac_pulse_period[18]} {dac_pulse_period[19]} {dac_pulse_period[20]} {dac_pulse_period[21]} {dac_pulse_period[22]} {dac_pulse_period[23]} {dac_pulse_period[24]} {dac_pulse_period[25]} {dac_pulse_period[26]} {dac_pulse_period[27]} {dac_pulse_period[28]} {dac_pulse_period[29]} {dac_pulse_period[30]} {dac_pulse_period[31]}]]
|
|
||||||
create_debug_port u_ila_1 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe4]
|
|
||||||
set_property port_width 32 [get_debug_ports u_ila_1/probe4]
|
|
||||||
connect_debug_port u_ila_1/probe4 [get_nets [list {dac_pulse_width[0]} {dac_pulse_width[1]} {dac_pulse_width[2]} {dac_pulse_width[3]} {dac_pulse_width[4]} {dac_pulse_width[5]} {dac_pulse_width[6]} {dac_pulse_width[7]} {dac_pulse_width[8]} {dac_pulse_width[9]} {dac_pulse_width[10]} {dac_pulse_width[11]} {dac_pulse_width[12]} {dac_pulse_width[13]} {dac_pulse_width[14]} {dac_pulse_width[15]} {dac_pulse_width[16]} {dac_pulse_width[17]} {dac_pulse_width[18]} {dac_pulse_width[19]} {dac_pulse_width[20]} {dac_pulse_width[21]} {dac_pulse_width[22]} {dac_pulse_width[23]} {dac_pulse_width[24]} {dac_pulse_width[25]} {dac_pulse_width[26]} {dac_pulse_width[27]} {dac_pulse_width[28]} {dac_pulse_width[29]} {dac_pulse_width[30]} {dac_pulse_width[31]}]]
|
|
||||||
create_debug_port u_ila_1 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe5]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_1/probe5]
|
|
||||||
connect_debug_port u_ila_1/probe5 [get_nets [list dac_rst]]
|
|
||||||
create_debug_port u_ila_1 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe6]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_1/probe6]
|
|
||||||
connect_debug_port u_ila_1/probe6 [get_nets [list dac_start]]
|
|
||||||
create_debug_core u_ila_2 ila
|
|
||||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2]
|
|
||||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2]
|
|
||||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2]
|
|
||||||
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_2]
|
|
||||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_2]
|
|
||||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2]
|
|
||||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_2]
|
|
||||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_2/clk]
|
|
||||||
connect_debug_port u_ila_2/clk [get_nets [list clk_wiz_ctrl_inst/inst/clk_out2]]
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe0]
|
|
||||||
set_property port_width 8 [get_debug_ports u_ila_2/probe0]
|
|
||||||
connect_debug_port u_ila_2/probe0 [get_nets [list {finish_cnt[0]} {finish_cnt[1]} {finish_cnt[2]} {finish_cnt[3]} {finish_cnt[4]} {finish_cnt[5]} {finish_cnt[6]} {finish_cnt[7]}]]
|
|
||||||
create_debug_port u_ila_2 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe1]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_2/probe1]
|
|
||||||
connect_debug_port u_ila_2/probe1 [get_nets [list finish_dbg]]
|
|
||||||
create_debug_port u_ila_2 probe
|
|
||||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe2]
|
|
||||||
set_property port_width 1 [get_debug_ports u_ila_2/probe2]
|
|
||||||
connect_debug_port u_ila_2/probe2 [get_nets [list finish_pending]]
|
|
||||||
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
|
|
||||||
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
|
|
||||||
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
|
|
||||||
connect_debug_port dbg_hub/clk [get_nets adc_clk]
|
|
||||||
@ -1,345 +0,0 @@
|
|||||||
`timescale 1 ns / 1 ns
|
|
||||||
|
|
||||||
module eth_generator_top #(
|
|
||||||
parameter int unsigned DAC_DATA_WIDTH = 14
|
|
||||||
)(
|
|
||||||
input sys_clk_p,
|
|
||||||
input sys_clk_n,
|
|
||||||
input rst_n,
|
|
||||||
|
|
||||||
output [3:0] led,
|
|
||||||
|
|
||||||
output e_reset,
|
|
||||||
output e_mdc,
|
|
||||||
inout e_mdio,
|
|
||||||
|
|
||||||
output [3:0] rgmii_txd,
|
|
||||||
output rgmii_txctl,
|
|
||||||
output rgmii_txc,
|
|
||||||
input [3:0] rgmii_rxd,
|
|
||||||
input rgmii_rxctl,
|
|
||||||
input rgmii_rxc,
|
|
||||||
|
|
||||||
// DAC
|
|
||||||
output p2_clk,
|
|
||||||
output p2_wrt,
|
|
||||||
(* MARK_DEBUG="true" *) output [13:0] p2_data
|
|
||||||
);
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// Internal GMII-side signals
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
wire [7:0] gmii_txd;
|
|
||||||
wire gmii_tx_en;
|
|
||||||
wire gmii_tx_er;
|
|
||||||
wire gmii_tx_clk;
|
|
||||||
wire gmii_crs;
|
|
||||||
wire gmii_col;
|
|
||||||
wire [7:0] gmii_rxd_i;
|
|
||||||
wire gmii_rx_dv;
|
|
||||||
wire gmii_rx_er;
|
|
||||||
wire gmii_rx_clk;
|
|
||||||
|
|
||||||
wire [31:0] pack_total_len;
|
|
||||||
|
|
||||||
wire e_rx_dv;
|
|
||||||
wire [7:0] e_rxd;
|
|
||||||
wire e_tx_en;
|
|
||||||
wire [7:0] e_txd;
|
|
||||||
wire e_rst_n;
|
|
||||||
wire sys_clk;
|
|
||||||
|
|
||||||
wire duplex_mode;
|
|
||||||
|
|
||||||
|
|
||||||
assign duplex_mode = 1'b1;
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// System clock buffer (200 MHz differential input)
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
IBUFDS sys_clk_ibufgds (
|
|
||||||
.O (sys_clk),
|
|
||||||
.I (sys_clk_p),
|
|
||||||
.IB (sys_clk_n)
|
|
||||||
);
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// IDELAYCTRL
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
(* IODELAY_GROUP = "rgmii_idelay_group" *)
|
|
||||||
IDELAYCTRL IDELAYCTRL_inst (
|
|
||||||
.RDY (),
|
|
||||||
.REFCLK (sys_clk),
|
|
||||||
.RST (1'b0)
|
|
||||||
);
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// Generated clocks for controller
|
|
||||||
// Need to create this IP in Vivado:
|
|
||||||
// input : 200 MHz
|
|
||||||
// output0: 130 MHz
|
|
||||||
// output1: 65 MHz
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
wire dac_clk;
|
|
||||||
wire adc_clk;
|
|
||||||
wire clk_wiz_locked;
|
|
||||||
|
|
||||||
clk_wiz_ctrl_inst clk_wiz_ctrl_inst (
|
|
||||||
.clk_in1 (sys_clk),
|
|
||||||
.reset (~rst_n),
|
|
||||||
.clk_out1 (dac_clk), // 130 MHz
|
|
||||||
.clk_out2 (adc_clk), // 65 MHz
|
|
||||||
.locked (clk_wiz_locked)
|
|
||||||
);
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// GMII <-> RGMII conversion
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
util_gmii_to_rgmii util_gmii_to_rgmii_m0 (
|
|
||||||
.reset (1'b0),
|
|
||||||
.rgmii_td (rgmii_txd),
|
|
||||||
.rgmii_tx_ctl (rgmii_txctl),
|
|
||||||
.rgmii_txc (rgmii_txc),
|
|
||||||
.rgmii_rd (rgmii_rxd),
|
|
||||||
.rgmii_rx_ctl (rgmii_rxctl),
|
|
||||||
.gmii_rx_clk (gmii_rx_clk),
|
|
||||||
.gmii_txd (e_txd),
|
|
||||||
.gmii_tx_en (e_tx_en),
|
|
||||||
.gmii_tx_er (1'b0),
|
|
||||||
.gmii_tx_clk (gmii_tx_clk),
|
|
||||||
.gmii_crs (gmii_crs),
|
|
||||||
.gmii_col (gmii_col),
|
|
||||||
.gmii_rxd (gmii_rxd_i),
|
|
||||||
.rgmii_rxc (rgmii_rxc),
|
|
||||||
.gmii_rx_dv (gmii_rx_dv),
|
|
||||||
.gmii_rx_er (gmii_rx_er),
|
|
||||||
.speed_selection (2'b10),
|
|
||||||
.duplex_mode (duplex_mode)
|
|
||||||
);
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// GMII arbitration / adaptation
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
gmii_arbi arbi_inst (
|
|
||||||
.clk (gmii_tx_clk),
|
|
||||||
.rst_n (rst_n),
|
|
||||||
.speed (2'b10),
|
|
||||||
.link (1'b1),
|
|
||||||
.pack_total_len (pack_total_len),
|
|
||||||
.e_rst_n (e_rst_n),
|
|
||||||
.gmii_rx_dv (gmii_rx_dv),
|
|
||||||
.gmii_rxd (gmii_rxd_i),
|
|
||||||
.gmii_tx_en (gmii_tx_en),
|
|
||||||
.gmii_txd (gmii_txd),
|
|
||||||
.e_rx_dv (e_rx_dv),
|
|
||||||
.e_rxd (e_rxd),
|
|
||||||
.e_tx_en (e_tx_en),
|
|
||||||
.e_txd (e_txd)
|
|
||||||
);
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// axis_mac interface
|
|
||||||
// RX stream from Ethernet goes into controller
|
|
||||||
// TX stream is unused for now
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
wire req_ready;
|
|
||||||
|
|
||||||
reg send_req;
|
|
||||||
reg [15:0] data_length;
|
|
||||||
|
|
||||||
reg [7:0] s_axis_tx_tdata;
|
|
||||||
reg s_axis_tx_tvalid;
|
|
||||||
wire s_axis_tx_tready;
|
|
||||||
reg s_axis_tx_tlast;
|
|
||||||
|
|
||||||
(* MARK_DEBUG="true" *) wire [7:0] m_axis_rx_tdata;
|
|
||||||
(* MARK_DEBUG="true" *) wire m_axis_rx_tvalid;
|
|
||||||
(* MARK_DEBUG="true" *) wire m_axis_rx_tlast;
|
|
||||||
(* MARK_DEBUG="true" *) wire m_axis_rx_tready;
|
|
||||||
|
|
||||||
// Always ready to accept RX payload bytes
|
|
||||||
assign m_axis_rx_tready = 1'b1;
|
|
||||||
|
|
||||||
// TX disabled
|
|
||||||
always @(*) begin
|
|
||||||
send_req = 1'b0;
|
|
||||||
data_length = 16'd0;
|
|
||||||
s_axis_tx_tdata = 8'd0;
|
|
||||||
s_axis_tx_tvalid= 1'b0;
|
|
||||||
s_axis_tx_tlast = 1'b0;
|
|
||||||
end
|
|
||||||
|
|
||||||
axis_mac axis_mac0 (
|
|
||||||
.gmii_tx_clk (gmii_tx_clk),
|
|
||||||
.gmii_rx_clk (gmii_rx_clk),
|
|
||||||
.rst_n (e_rst_n),
|
|
||||||
|
|
||||||
.gmii_rx_dv (e_rx_dv),
|
|
||||||
.gmii_rxd (e_rxd),
|
|
||||||
.gmii_tx_en (gmii_tx_en),
|
|
||||||
.gmii_txd (gmii_txd),
|
|
||||||
|
|
||||||
.send_req (send_req),
|
|
||||||
.data_length (data_length),
|
|
||||||
.req_ready (req_ready),
|
|
||||||
|
|
||||||
.s_axis_tx_tdata (s_axis_tx_tdata),
|
|
||||||
.s_axis_tx_tvalid (s_axis_tx_tvalid),
|
|
||||||
.s_axis_tx_tready (s_axis_tx_tready),
|
|
||||||
.s_axis_tx_tlast (s_axis_tx_tlast),
|
|
||||||
|
|
||||||
.m_axis_rx_tdata (m_axis_rx_tdata),
|
|
||||||
.m_axis_rx_tvalid (m_axis_rx_tvalid),
|
|
||||||
.m_axis_rx_tready (m_axis_rx_tready),
|
|
||||||
.m_axis_rx_tlast (m_axis_rx_tlast)
|
|
||||||
);
|
|
||||||
|
|
||||||
// PHY reset helper from your original example
|
|
||||||
reset reset_m0 (
|
|
||||||
.clk (sys_clk),
|
|
||||||
.key1 (rst_n),
|
|
||||||
.rst_n (e_reset)
|
|
||||||
);
|
|
||||||
|
|
||||||
// MDIO lines are not driven here yet
|
|
||||||
assign e_mdc = 1'b0;
|
|
||||||
assign e_mdio = 1'bz;
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// Controller reset
|
|
||||||
// Use both external reset and clk_wiz lock
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
wire ctrl_rst_n = rst_n & clk_wiz_locked;
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// Debug finish generator (still used here, since generator doesn't have finish signal)
|
|
||||||
//
|
|
||||||
// After each adc_start pulse generates one finish pulse after some delay.
|
|
||||||
// This is just for first bring-up so the controller can leave busy state
|
|
||||||
// If you don't want this, replace with:
|
|
||||||
// wire finish_dbg = 1'b0;
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
(* MARK_DEBUG="true" *) logic finish_dbg;
|
|
||||||
(* MARK_DEBUG="true" *) logic [7:0] finish_cnt;
|
|
||||||
(* MARK_DEBUG="true" *) logic finish_pending;
|
|
||||||
|
|
||||||
// Controller outputs to debug
|
|
||||||
(* MARK_DEBUG="true" *) wire [31:0] dac_pulse_width;
|
|
||||||
(* MARK_DEBUG="true" *) wire [31:0] dac_pulse_period;
|
|
||||||
(* MARK_DEBUG="true" *) wire [DAC_DATA_WIDTH-1:0] dac_pulse_height;
|
|
||||||
(* MARK_DEBUG="true" *) wire [15:0] dac_pulse_num;
|
|
||||||
|
|
||||||
(* MARK_DEBUG="true" *) wire [31:0] adc_pulse_period_dbg;
|
|
||||||
(* MARK_DEBUG="true" *) wire [15:0] adc_pulse_num_dbg;
|
|
||||||
|
|
||||||
(* MARK_DEBUG="true" *) wire dac_start;
|
|
||||||
(* MARK_DEBUG="true" *) wire adc_start_dbg;
|
|
||||||
(* MARK_DEBUG="true" *) wire dac_rst;
|
|
||||||
(* MARK_DEBUG="true" *) wire adc_rst_dbg;
|
|
||||||
|
|
||||||
always_ff @(posedge adc_clk or negedge ctrl_rst_n) begin
|
|
||||||
if (!ctrl_rst_n) begin
|
|
||||||
finish_dbg <= 1'b0;
|
|
||||||
finish_cnt <= 8'd0;
|
|
||||||
finish_pending <= 1'b0;
|
|
||||||
end else begin
|
|
||||||
finish_dbg <= 1'b0;
|
|
||||||
|
|
||||||
if (adc_start_dbg) begin
|
|
||||||
finish_pending <= 1'b1;
|
|
||||||
finish_cnt <= 8'd80;
|
|
||||||
end else if (finish_pending) begin
|
|
||||||
if (finish_cnt == 8'd0) begin
|
|
||||||
finish_dbg <= 1'b1;
|
|
||||||
finish_pending <= 1'b0;
|
|
||||||
end else begin
|
|
||||||
finish_cnt <= finish_cnt - 8'd1;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// Controller
|
|
||||||
// ETH domain = gmii_rx_clk, because RX AXI master comes from axis_mac RX side
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
control #(
|
|
||||||
.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
|
|
||||||
) udp_ctrl_inst (
|
|
||||||
.eth_clk_in (gmii_rx_clk),
|
|
||||||
.dac_clk_in (dac_clk),
|
|
||||||
.adc_clk_in (adc_clk),
|
|
||||||
.rst_n (ctrl_rst_n),
|
|
||||||
|
|
||||||
.s_axis_tdata (m_axis_rx_tdata),
|
|
||||||
.s_axis_tvalid (m_axis_rx_tvalid),
|
|
||||||
.s_axis_tready (), // controller internally always ready in current version
|
|
||||||
.s_axis_tlast (m_axis_rx_tlast),
|
|
||||||
|
|
||||||
.finish (finish_dbg),
|
|
||||||
|
|
||||||
.dac_pulse_width (dac_pulse_width),
|
|
||||||
.dac_pulse_period (dac_pulse_period),
|
|
||||||
.dac_pulse_height (dac_pulse_height),
|
|
||||||
.dac_pulse_num (dac_pulse_num),
|
|
||||||
|
|
||||||
.adc_pulse_period (adc_pulse_period_dbg),
|
|
||||||
.adc_pulse_num (adc_pulse_num_dbg),
|
|
||||||
|
|
||||||
.dac_start (dac_start),
|
|
||||||
.adc_start (adc_start_dbg),
|
|
||||||
|
|
||||||
.dac_rst (dac_rst),
|
|
||||||
.adc_rst (adc_rst_dbg)
|
|
||||||
);
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// DAC
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
generator #(
|
|
||||||
.DATA_WIDTH(DAC_DATA_WIDTH)
|
|
||||||
) generator_inst (
|
|
||||||
.clk_in(dac_clk),
|
|
||||||
.rst(dac_rst),
|
|
||||||
.start(dac_start),
|
|
||||||
.pulse_width(dac_pulse_width),
|
|
||||||
.pulse_period(dac_pulse_period),
|
|
||||||
.pulse_height(dac_pulse_height),
|
|
||||||
.pulse_num(dac_pulse_num),
|
|
||||||
.pulse(p2_wrt ),
|
|
||||||
.pulse_height_out(p2_data)
|
|
||||||
);
|
|
||||||
|
|
||||||
// dac clk mgt
|
|
||||||
wire p2_clk_oddr;
|
|
||||||
|
|
||||||
ODDR #(
|
|
||||||
.DDR_CLK_EDGE("SAME_EDGE"),
|
|
||||||
.INIT(1'b0),
|
|
||||||
.SRTYPE("SYNC")
|
|
||||||
) ODDR_p2_clk (
|
|
||||||
.Q (p2_clk_oddr),
|
|
||||||
.C (dac_clk),
|
|
||||||
.CE(1'b1),
|
|
||||||
.D1(1'b1),
|
|
||||||
.D2(1'b0),
|
|
||||||
.R (1'b0),
|
|
||||||
.S (1'b0)
|
|
||||||
);
|
|
||||||
|
|
||||||
OBUF OBUF_p2_clk (
|
|
||||||
.I(p2_clk_oddr),
|
|
||||||
.O(p2_clk)
|
|
||||||
);
|
|
||||||
|
|
||||||
//assign p2_wrt = p2_clk;
|
|
||||||
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
// Simple LED status
|
|
||||||
// -------------------------------------------------------------------------
|
|
||||||
assign led[0] = clk_wiz_locked;
|
|
||||||
assign led[1] = m_axis_rx_tvalid;
|
|
||||||
assign led[2] = dac_start;
|
|
||||||
assign led[3] = adc_rst_dbg;
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
@ -1,689 +0,0 @@
|
|||||||
{
|
|
||||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
|
||||||
"ip_inst": {
|
|
||||||
"xci_name": "clk_wiz_ctrl_inst",
|
|
||||||
"component_reference": "xilinx.com:ip:clk_wiz:6.0",
|
|
||||||
"ip_revision": "16",
|
|
||||||
"gen_directory": "../../../../eth_generator_top.gen/sources_1/ip/clk_wiz_ctrl_inst",
|
|
||||||
"parameters": {
|
|
||||||
"component_parameters": {
|
|
||||||
"Component_Name": [ { "value": "clk_wiz_ctrl_inst", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PRIM_IN_FREQ": [ { "value": "200.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKIN1_JITTER_PS": [ { "value": "50.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"NUM_OUT_CLKS": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "65.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"USE_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"MMCM_DIVCLK_DIVIDE": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"MMCM_CLKFBOUT_MULT_F": [ { "value": "16.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT0_DIVIDE_F": [ { "value": "6.750", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT1_DIVIDE": [ { "value": "13", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
|
||||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT1_JITTER": [ { "value": "162.582", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT1_PHASE_ERROR": [ { "value": "137.238", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT2_JITTER": [ { "value": "185.296", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT2_PHASE_ERROR": [ { "value": "137.238", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT4_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT4_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
|
||||||
"INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
|
|
||||||
"AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
|
||||||
"PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
|
||||||
},
|
|
||||||
"model_parameters": {
|
|
||||||
"C_CLKOUT2_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"c_component_name": [ { "value": "clk_wiz_ctrl_inst", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_PHASE_ALIGNMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PRIM_IN_FREQ": [ { "value": "200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_USE_RESET": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_NUM_OUT_CLKS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_INCLK_SUM_ROW0": [ { "value": "Input Clock Freq (MHz) Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_INCLK_SUM_ROW1": [ { "value": "__primary_________200.000____________0.010", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__125.00000______0.000______50.0______162.582____137.238", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__64.90385______0.000______50.0______185.296____137.238", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "125", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "65.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_OUT_FREQ": [ { "value": "125.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_OUT_FREQ": [ { "value": "64.90385", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKFBOUT_MULT_F": [ { "value": "16.875", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKIN1_PERIOD": [ { "value": "5.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
|
||||||
"C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_DIVCLK_DIVIDE": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "6.750", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT1_DIVIDE": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKIN1_JITTER_PS": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
|
||||||
"C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIVIDE2_AUTO": [ { "value": "1.9259259259259258", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIVIDE3_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIVIDE4_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIVIDE5_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIVIDE6_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_DIVIDE7_AUTO": [ { "value": "0.14814814814814814", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT0_ACTUAL_FREQ": [ { "value": "125.00000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT1_ACTUAL_FREQ": [ { "value": "64.90385", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
|
||||||
"C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_D_MAX": [ { "value": "80.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_VCO_MIN": [ { "value": "600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
|
||||||
"C_VCO_MAX": [ { "value": "1200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
|
|
||||||
},
|
|
||||||
"project_parameters": {
|
|
||||||
"ARCHITECTURE": [ { "value": "artix7" } ],
|
|
||||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
|
||||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
|
||||||
"DEVICE": [ { "value": "xc7a35t" } ],
|
|
||||||
"PACKAGE": [ { "value": "fgg484" } ],
|
|
||||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
|
||||||
"SILICON_REVISION": [ { "value": "" } ],
|
|
||||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
|
||||||
"SPEEDGRADE": [ { "value": "-1" } ],
|
|
||||||
"STATIC_POWER": [ { "value": "" } ],
|
|
||||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
|
||||||
},
|
|
||||||
"runtime_parameters": {
|
|
||||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
|
||||||
"IPREVISION": [ { "value": "16" } ],
|
|
||||||
"MANAGED": [ { "value": "TRUE" } ],
|
|
||||||
"OUTPUTDIR": [ { "value": "../../../../eth_generator_top.gen/sources_1/ip/clk_wiz_ctrl_inst" } ],
|
|
||||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
|
||||||
"SHAREDDIR": [ { "value": "." } ],
|
|
||||||
"SWVERSION": [ { "value": "2025.1" } ],
|
|
||||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"boundary": {
|
|
||||||
"ports": {
|
|
||||||
"reset": [ { "direction": "in", "driver_value": "0" } ],
|
|
||||||
"clk_in1": [ { "direction": "in" } ],
|
|
||||||
"clk_out1": [ { "direction": "out" } ],
|
|
||||||
"clk_out2": [ { "direction": "out" } ],
|
|
||||||
"locked": [ { "direction": "out" } ]
|
|
||||||
},
|
|
||||||
"interfaces": {
|
|
||||||
"reset": {
|
|
||||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
|
||||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
|
||||||
"mode": "slave",
|
|
||||||
"parameters": {
|
|
||||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
|
|
||||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "usage": "all" } ],
|
|
||||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
|
||||||
},
|
|
||||||
"port_maps": {
|
|
||||||
"RST": [ { "physical_name": "reset" } ]
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"clock_CLK_IN1": {
|
|
||||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
|
||||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
|
||||||
"mode": "slave",
|
|
||||||
"parameters": {
|
|
||||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ]
|
|
||||||
},
|
|
||||||
"port_maps": {
|
|
||||||
"CLK_IN1": [ { "physical_name": "clk_in1" } ]
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"clock_CLK_OUT1": {
|
|
||||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
|
||||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
|
||||||
"mode": "master",
|
|
||||||
"parameters": {
|
|
||||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
|
||||||
},
|
|
||||||
"port_maps": {
|
|
||||||
"CLK_OUT1": [ { "physical_name": "clk_out1" } ]
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"clock_CLK_OUT2": {
|
|
||||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
|
||||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
|
||||||
"mode": "master",
|
|
||||||
"parameters": {
|
|
||||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
|
||||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
|
||||||
},
|
|
||||||
"port_maps": {
|
|
||||||
"CLK_OUT2": [ { "physical_name": "clk_out2" } ]
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
145
designs/reflectometer_base/README.md
Normal file
145
designs/reflectometer_base/README.md
Normal file
@ -0,0 +1,145 @@
|
|||||||
|
# Рефлектометр
|
||||||
|
|
||||||
|
Модуль представляет собой законченную встраиваемую систему рефлектометра, объединяющую:
|
||||||
|
|
||||||
|
- контроллер управления
|
||||||
|
- генератор импульсов (DAC path)
|
||||||
|
- сэмплер данных (ADC path)
|
||||||
|
- аккумулятор и обработчик данных
|
||||||
|
|
||||||
|
Система предназначена для формирования импульсов, синхронного сбора отраженного сигнала, накопления результатов и передачи обработанных данных во внешнюю систему.
|
||||||
|
|
||||||
|
Данный модуль является полноценным интегрируемым блоком, который может использоваться как самостоятельная аппаратная подсистема внутри более крупного проекта.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## Назначение системы
|
||||||
|
|
||||||
|
Основная задача системы:
|
||||||
|
|
||||||
|
1. Получить параметры измерения через AXI Stream
|
||||||
|
2. Сформировать последовательность импульсов на DAC
|
||||||
|
3. Выполнить синходную выборку данных с ADC
|
||||||
|
4. Накопить и обработать результаты
|
||||||
|
5. Передать итоговые данные обратно через AXI Stream
|
||||||
|
|
||||||
|
Таким образом реализуется полный цикл измерения без необходимости внешнего управления отдельными блоками.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## Состав системы
|
||||||
|
|
||||||
|
### Controller
|
||||||
|
|
||||||
|
Принимает входные команды по AXI Stream (Ethernet RX), декодирует параметры измерения и управляет всеми внутренними модулями системы.
|
||||||
|
|
||||||
|
Формирует:
|
||||||
|
|
||||||
|
- запуск генератора (`dac_start`)
|
||||||
|
- запуск аккумулятора (`adc_start`)
|
||||||
|
- параметры импульсов DAC
|
||||||
|
- параметры выборки ADC
|
||||||
|
- локальные reset-сигналы
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
### Generator
|
||||||
|
|
||||||
|
Формирует последовательность импульсов на DAC с заданными:
|
||||||
|
|
||||||
|
- амплитудой
|
||||||
|
- длительностью
|
||||||
|
- периодом
|
||||||
|
- количеством повторений
|
||||||
|
|
||||||
|
Для каждого импульса инициирует запуск выборки в сэмплере.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
### Sampler
|
||||||
|
|
||||||
|
Выполняет синхронный сбор данных с ADC по запросу генератора.
|
||||||
|
|
||||||
|
Поддерживает:
|
||||||
|
|
||||||
|
- фильтрацию `out_of_range`
|
||||||
|
- упаковку данных
|
||||||
|
- преобразование типа кода ( прямой или дополнительный)
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
### Accumulator
|
||||||
|
|
||||||
|
Получает поток данных от сэмплера, выполняет накопление, усреднение и оконную обработку, после чего формирует пакеты для передачи результата.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## Управление системой
|
||||||
|
|
||||||
|
Пользователь взаимодействует только с контроллером через AXI Stream-интерфейс.
|
||||||
|
|
||||||
|
Прямое управление генератором, сэмплером и аккумулятором не требуется.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## Clock Domain Crossing (CDC)
|
||||||
|
|
||||||
|
Система работает в нескольких тактовых доменах:
|
||||||
|
|
||||||
|
- Ethernet RX (`gmii_rx_clk`)
|
||||||
|
- Ethernet TX (`gmii_tx_clk`)
|
||||||
|
- DAC (`dac_clk`)
|
||||||
|
- ADC (`adc_clk`)
|
||||||
|
|
||||||
|
Для корректной синхронизации между DAC и ADC используются специальные CDC-регистры для сигналов:
|
||||||
|
|
||||||
|
- `sample_req`
|
||||||
|
- `sample_done`
|
||||||
|
|
||||||
|
Это обеспечивает безопасную передачу handshake-сигналов между тактовыми доменами.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## Список параметров
|
||||||
|
|
||||||
|
### DAC_DATA_WIDTH
|
||||||
|
Ширина выходных данных отправляемых на ЦАП.
|
||||||
|
|
||||||
|
### ZERO_LEVEL
|
||||||
|
Уровень сигнала в состоянии отсутствия импульса (базовый уровень сигнала).
|
||||||
|
|
||||||
|
Типовые значения:
|
||||||
|
|
||||||
|
- `8192` — середина диапазона ЦАП
|
||||||
|
- `0` — нулевой уровень
|
||||||
|
|
||||||
|
### ADC_DATA_WIDTH
|
||||||
|
Ширина входных данных, получаемых с АЦП.
|
||||||
|
|
||||||
|
### PACK_FACTOR
|
||||||
|
Количество отсчетов, собираемых в один выходной пакет.
|
||||||
|
|
||||||
|
### PROCESS_MODE
|
||||||
|
Режим интерпретации входного кода:
|
||||||
|
|
||||||
|
- `0` — прямой код
|
||||||
|
- `1` — дополнительный код
|
||||||
|
|
||||||
|
### ACCUM_WIDTH
|
||||||
|
Размер данных для аккумуляции, должен быть степенью числа 2. По умолчанию - 32
|
||||||
|
|
||||||
|
### N_MAX
|
||||||
|
Максимальное число окон в последовательности. Должно быть степенью числа 2. Влияет на размер используемой памяти.
|
||||||
|
|
||||||
|
### WINDOW_SIZE
|
||||||
|
Размер окна усреднения
|
||||||
|
|
||||||
|
### PACKET_SIZE
|
||||||
|
Размер выходного пакета
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## Сборка
|
||||||
|
```make all``` - собрать все до битстрима
|
||||||
|
|
||||||
|
```make vivado``` - открыть проект в Vivado
|
||||||
@ -5,6 +5,7 @@ module reflectometer_top #(
|
|||||||
parameter int unsigned ADC_DATA_WIDTH = 12,
|
parameter int unsigned ADC_DATA_WIDTH = 12,
|
||||||
parameter PACK_FACTOR = 1,
|
parameter PACK_FACTOR = 1,
|
||||||
parameter PROCESS_MODE = 0,
|
parameter PROCESS_MODE = 0,
|
||||||
|
parameter ZERO_LEVEL = 8192,
|
||||||
parameter ACCUM_WIDTH = 32,
|
parameter ACCUM_WIDTH = 32,
|
||||||
parameter N_MAX = 4096,
|
parameter N_MAX = 4096,
|
||||||
parameter WINDOW_SIZE = 65,
|
parameter WINDOW_SIZE = 65,
|
||||||
@ -191,7 +192,8 @@ module reflectometer_top #(
|
|||||||
//------------------------------------------------------------
|
//------------------------------------------------------------
|
||||||
|
|
||||||
generator #(
|
generator #(
|
||||||
.DATA_WIDTH(DAC_DATA_WIDTH)
|
.DATA_WIDTH(DAC_DATA_WIDTH),
|
||||||
|
.ZERO_LEVEL(ZERO_LEVEL)
|
||||||
) generator_inst (
|
) generator_inst (
|
||||||
.clk_in(dac_clk),
|
.clk_in(dac_clk),
|
||||||
.rst(dac_rst),
|
.rst(dac_rst),
|
||||||
|
|||||||
@ -1,11 +1,13 @@
|
|||||||
# Тестовый проект Generator + ETH + CTRL
|
# Тестовый проект рефлектометра
|
||||||
Проект состоит из AXIS Ethernet, контроллера и генератора. Позволяет генерировать сигналы, задав параметры через Ethernet.
|
Проект состоит из AXIS Ethernet и основной части рефлектометра - генератора, сэмплера, контроллера и синхронизирующей логики. Разработан для AX7102, АЦП AN9238, ЦАП AD9767. Плата подключается по ethernet к компьютеру, IP должен быть 192.168.0.3 у компьютера, в ПЛИС установлен IP 192.168.0.2, после подключения должен пройти ARP и после этого можно начнить коммуникацию через консольку.
|
||||||
## Сборка
|
## Сборка
|
||||||
```make all``` - собрать все до битстрима
|
```make all``` - собрать все до битстрима
|
||||||
|
|
||||||
```make vivado``` - открыть проект в Vivado
|
```make vivado``` - открыть проект в Vivado
|
||||||
|
|
||||||
## Управление
|
## Управление
|
||||||
Используйте software/console.py. Пример:
|
Используйте software/console.py. Примеры:
|
||||||
|
|
||||||
```python3 console.py --pulse_width 3_500_000 --pulse_period 20_000_000 --pulse_height 10000 --pulse_num 5500 --dac-bits 14```
|
```python3 console.py --pulse_width 3500 --pulse_period 20000 --pulse_height 15000 --pulse_num 550 --dac-bits 14```
|
||||||
|
|
||||||
|
```python3 console.py --pulse_width 15000 --pulse_period 20000 --pulse_height 1500 --pulse_num 550 --dac-bits 14```
|
||||||
@ -5,6 +5,7 @@ module prototype_top #(
|
|||||||
parameter int unsigned ADC_DATA_WIDTH = 12,
|
parameter int unsigned ADC_DATA_WIDTH = 12,
|
||||||
parameter PACK_FACTOR = 1,
|
parameter PACK_FACTOR = 1,
|
||||||
parameter PROCESS_MODE = 0,
|
parameter PROCESS_MODE = 0,
|
||||||
|
parameter ZERO_LEVEL = 8192,
|
||||||
parameter ACCUM_WIDTH = 32,
|
parameter ACCUM_WIDTH = 32,
|
||||||
parameter N_MAX = 4096,
|
parameter N_MAX = 4096,
|
||||||
parameter WINDOW_SIZE = 65,
|
parameter WINDOW_SIZE = 65,
|
||||||
@ -131,6 +132,7 @@ module prototype_top #(
|
|||||||
.PACK_FACTOR(PACK_FACTOR),
|
.PACK_FACTOR(PACK_FACTOR),
|
||||||
.ACCUM_WIDTH(ACCUM_WIDTH),
|
.ACCUM_WIDTH(ACCUM_WIDTH),
|
||||||
.N_MAX(N_MAX),
|
.N_MAX(N_MAX),
|
||||||
|
.ZERO_LEVEL(ZERO_LEVEL),
|
||||||
.WINDOW_SIZE(WINDOW_SIZE),
|
.WINDOW_SIZE(WINDOW_SIZE),
|
||||||
.PACKET_SIZE(PACKET_SIZE),
|
.PACKET_SIZE(PACKET_SIZE),
|
||||||
.ADC_DATA_WIDTH(ADC_DATA_WIDTH),
|
.ADC_DATA_WIDTH(ADC_DATA_WIDTH),
|
||||||
|
|||||||
@ -1 +0,0 @@
|
|||||||
# Блок Sampler
|
|
||||||
1
libs/rtl_libs
Submodule
1
libs/rtl_libs
Submodule
Submodule libs/rtl_libs added at 338f30c0d7
1
libs/verilog-axi
Submodule
1
libs/verilog-axi
Submodule
Submodule libs/verilog-axi added at 516bd5dadc
@ -11,13 +11,13 @@
|
|||||||
</db_ref>
|
</db_ref>
|
||||||
</db_ref_list>
|
</db_ref_list>
|
||||||
<zoom_setting>
|
<zoom_setting>
|
||||||
<ZoomStartTime time="0.000000 us"></ZoomStartTime>
|
<ZoomStartTime time="2,748,541.000 ns"></ZoomStartTime>
|
||||||
<ZoomEndTime time="16.740001 us"></ZoomEndTime>
|
<ZoomEndTime time="2,749,382.001 ns"></ZoomEndTime>
|
||||||
<Cursor1Time time="6.500000 us"></Cursor1Time>
|
<Cursor1Time time="2,749,045.000 ns"></Cursor1Time>
|
||||||
</zoom_setting>
|
</zoom_setting>
|
||||||
<column_width_setting>
|
<column_width_setting>
|
||||||
<NameColumnWidth column_width="556"></NameColumnWidth>
|
<NameColumnWidth column_width="556"></NameColumnWidth>
|
||||||
<ValueColumnWidth column_width="111"></ValueColumnWidth>
|
<ValueColumnWidth column_width="107"></ValueColumnWidth>
|
||||||
</column_width_setting>
|
</column_width_setting>
|
||||||
<WVObjectSize size="18" />
|
<WVObjectSize size="18" />
|
||||||
<wvobject type="logic" fp_name="/tb_accumulator_top/clk_in">
|
<wvobject type="logic" fp_name="/tb_accumulator_top/clk_in">
|
||||||
@ -116,6 +116,10 @@
|
|||||||
<obj_property name="ElementShortName">addrb[15:0]</obj_property>
|
<obj_property name="ElementShortName">addrb[15:0]</obj_property>
|
||||||
<obj_property name="ObjectShortName">addrb[15:0]</obj_property>
|
<obj_property name="ObjectShortName">addrb[15:0]</obj_property>
|
||||||
</wvobject>
|
</wvobject>
|
||||||
|
<wvobject type="array" fp_name="/tb_accumulator_top/dut/accum_main/wr_state">
|
||||||
|
<obj_property name="ElementShortName">wr_state[3:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">wr_state[3:0]</obj_property>
|
||||||
|
</wvobject>
|
||||||
</wvobject>
|
</wvobject>
|
||||||
<wvobject type="group" fp_name="group27">
|
<wvobject type="group" fp_name="group27">
|
||||||
<obj_property name="label">fifo</obj_property>
|
<obj_property name="label">fifo</obj_property>
|
||||||
@ -166,13 +170,13 @@
|
|||||||
<obj_property name="ObjectShortName">PROG_FULL_THRESH[31:0]</obj_property>
|
<obj_property name="ObjectShortName">PROG_FULL_THRESH[31:0]</obj_property>
|
||||||
</wvobject>
|
</wvobject>
|
||||||
<wvobject type="array" fp_name="/tb_accumulator_top/dut/output_async_fifo/xpm_fifo_async_inst/wr_data_count">
|
<wvobject type="array" fp_name="/tb_accumulator_top/dut/output_async_fifo/xpm_fifo_async_inst/wr_data_count">
|
||||||
<obj_property name="ElementShortName">wr_data_count[4:0]</obj_property>
|
<obj_property name="ElementShortName">wr_data_count[9:0]</obj_property>
|
||||||
<obj_property name="ObjectShortName">wr_data_count[4:0]</obj_property>
|
<obj_property name="ObjectShortName">wr_data_count[9:0]</obj_property>
|
||||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||||
</wvobject>
|
</wvobject>
|
||||||
<wvobject type="array" fp_name="/tb_accumulator_top/dut/output_async_fifo/xpm_fifo_async_inst/rd_data_count">
|
<wvobject type="array" fp_name="/tb_accumulator_top/dut/output_async_fifo/xpm_fifo_async_inst/rd_data_count">
|
||||||
<obj_property name="ElementShortName">rd_data_count[6:0]</obj_property>
|
<obj_property name="ElementShortName">rd_data_count[11:0]</obj_property>
|
||||||
<obj_property name="ObjectShortName">rd_data_count[6:0]</obj_property>
|
<obj_property name="ObjectShortName">rd_data_count[11:0]</obj_property>
|
||||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||||
</wvobject>
|
</wvobject>
|
||||||
</wvobject>
|
</wvobject>
|
||||||
|
|||||||
@ -41,14 +41,15 @@
|
|||||||
|
|
||||||
*start* отправляет пульс start на dac_start и adc_start в их доменах. при этом после этого блок перестает быть ready и ждет, пока не придет пульс finish, после этого он возвращается снова в *idle* состояние
|
*start* отправляет пульс start на dac_start и adc_start в их доменах. при этом после этого блок перестает быть ready и ждет, пока не придет пульс finish, после этого он возвращается снова в *idle* состояние
|
||||||
|
|
||||||
*set_data* значит, что следующие 96 бит = 12*8 байт, пришедшии по axis - это конфигурационная информация и ее нужно записать в внутренний регистр на 96 бит.
|
*set_data* значит, что следующие 128 бит = 16*8 байт, пришедшии по axis - это конфигурационная информация и ее нужно записать в внутренний регистр на 128 бит.
|
||||||
|
|
||||||
конфигурационный регистр на 96 бит делится так:
|
конфигурационный регистр на 128 бит делится так:
|
||||||
```
|
```
|
||||||
reg[31:0] - pulse_width
|
reg[31:0] - pulse_width
|
||||||
reg[63:32] - pulse_period
|
reg[63:32] - pulse_period
|
||||||
reg[79:64] - pulse_num
|
reg[79:64] - pulse_num
|
||||||
reg[79+dac_data_width:80] - pulse_height
|
reg[79+dac_data_width:80] - pulse_height
|
||||||
|
reg[127:96] - pulse_period_adc
|
||||||
```
|
```
|
||||||
|
|
||||||
соотвественно эти записанные значения выставляются на соотвествующие выходные сигналы в доменах dac_clk и adc_clk. выходы обновляются каждый раз, когда происходит set_data, и сигналы сохраняют своё значение до следующего set_data.
|
соотвественно эти записанные значения выставляются на соотвествующие выходные сигналы в доменах dac_clk и adc_clk. выходы обновляются каждый раз, когда происходит set_data, и сигналы сохраняют своё значение до следующего set_data.
|
||||||
|
|||||||
197
rtl/controller/tests/tb_control_behav.wcfg
Normal file
197
rtl/controller/tests/tb_control_behav.wcfg
Normal file
@ -0,0 +1,197 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<wave_config>
|
||||||
|
<wave_state>
|
||||||
|
</wave_state>
|
||||||
|
<db_ref_list>
|
||||||
|
<db_ref path="tb_control_behav.wdb" id="1">
|
||||||
|
<top_modules>
|
||||||
|
<top_module name="glbl" />
|
||||||
|
<top_module name="tb_control" />
|
||||||
|
</top_modules>
|
||||||
|
</db_ref>
|
||||||
|
</db_ref_list>
|
||||||
|
<zoom_setting>
|
||||||
|
<ZoomStartTime time="0.676 ns"></ZoomStartTime>
|
||||||
|
<ZoomEndTime time="645.677 ns"></ZoomEndTime>
|
||||||
|
<Cursor1Time time="349.676 ns"></Cursor1Time>
|
||||||
|
</zoom_setting>
|
||||||
|
<column_width_setting>
|
||||||
|
<NameColumnWidth column_width="558"></NameColumnWidth>
|
||||||
|
<ValueColumnWidth column_width="61"></ValueColumnWidth>
|
||||||
|
</column_width_setting>
|
||||||
|
<WVObjectSize size="23" />
|
||||||
|
<wvobject type="logic" fp_name="/tb_control/eth_clk_in">
|
||||||
|
<obj_property name="ElementShortName">eth_clk_in</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">eth_clk_in</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#008080</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="logic" fp_name="/tb_control/dac_clk_in">
|
||||||
|
<obj_property name="ElementShortName">dac_clk_in</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">dac_clk_in</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="logic" fp_name="/tb_control/adc_clk_in">
|
||||||
|
<obj_property name="ElementShortName">adc_clk_in</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">adc_clk_in</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="logic" fp_name="/tb_control/rst_n">
|
||||||
|
<obj_property name="ElementShortName">rst_n</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">rst_n</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#800080</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="array" fp_name="/tb_control/s_axis_tdata">
|
||||||
|
<obj_property name="ElementShortName">s_axis_tdata[7:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">s_axis_tdata[7:0]</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#008080</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
<obj_property name="Radix">BINARYRADIX</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="logic" fp_name="/tb_control/s_axis_tvalid">
|
||||||
|
<obj_property name="ElementShortName">s_axis_tvalid</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">s_axis_tvalid</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#008080</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="logic" fp_name="/tb_control/s_axis_tready">
|
||||||
|
<obj_property name="ElementShortName">s_axis_tready</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">s_axis_tready</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#008080</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="logic" fp_name="/tb_control/s_axis_tlast">
|
||||||
|
<obj_property name="ElementShortName">s_axis_tlast</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">s_axis_tlast</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#008080</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="logic" fp_name="/tb_control/finish">
|
||||||
|
<obj_property name="ElementShortName">finish</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">finish</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#FAAFBE</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="array" fp_name="/tb_control/dac_pulse_width">
|
||||||
|
<obj_property name="ElementShortName">dac_pulse_width[31:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">dac_pulse_width[31:0]</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="array" fp_name="/tb_control/dac_pulse_period">
|
||||||
|
<obj_property name="ElementShortName">dac_pulse_period[31:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">dac_pulse_period[31:0]</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="array" fp_name="/tb_control/dac_pulse_height">
|
||||||
|
<obj_property name="ElementShortName">dac_pulse_height[11:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">dac_pulse_height[11:0]</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="array" fp_name="/tb_control/dac_pulse_num">
|
||||||
|
<obj_property name="ElementShortName">dac_pulse_num[15:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">dac_pulse_num[15:0]</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="array" fp_name="/tb_control/adc_pulse_period">
|
||||||
|
<obj_property name="ElementShortName">adc_pulse_period[31:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">adc_pulse_period[31:0]</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="array" fp_name="/tb_control/adc_pulse_num">
|
||||||
|
<obj_property name="ElementShortName">adc_pulse_num[15:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">adc_pulse_num[15:0]</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="logic" fp_name="/tb_control/dac_start">
|
||||||
|
<obj_property name="ElementShortName">dac_start</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">dac_start</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="logic" fp_name="/tb_control/adc_start">
|
||||||
|
<obj_property name="ElementShortName">adc_start</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">adc_start</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="logic" fp_name="/tb_control/dac_rst">
|
||||||
|
<obj_property name="ElementShortName">dac_rst</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">dac_rst</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#FFA500</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="logic" fp_name="/tb_control/adc_rst">
|
||||||
|
<obj_property name="ElementShortName">adc_rst</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">adc_rst</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="group" fp_name="group499">
|
||||||
|
<obj_property name="label">tb signals</obj_property>
|
||||||
|
<obj_property name="DisplayName">label</obj_property>
|
||||||
|
<wvobject type="array" fp_name="/tb_control/dac_rst_count">
|
||||||
|
<obj_property name="ElementShortName">dac_rst_count[31:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">dac_rst_count[31:0]</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="array" fp_name="/tb_control/adc_rst_count">
|
||||||
|
<obj_property name="ElementShortName">adc_rst_count[31:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">adc_rst_count[31:0]</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="array" fp_name="/tb_control/dac_start_count">
|
||||||
|
<obj_property name="ElementShortName">dac_start_count[31:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">dac_start_count[31:0]</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="array" fp_name="/tb_control/adc_start_count">
|
||||||
|
<obj_property name="ElementShortName">adc_start_count[31:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">adc_start_count[31:0]</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="array" fp_name="/tb_control/test_pulse_width">
|
||||||
|
<obj_property name="ElementShortName">test_pulse_width[31:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">test_pulse_width[31:0]</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="array" fp_name="/tb_control/test_pulse_period">
|
||||||
|
<obj_property name="ElementShortName">test_pulse_period[31:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">test_pulse_period[31:0]</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="array" fp_name="/tb_control/test_pulse_num">
|
||||||
|
<obj_property name="ElementShortName">test_pulse_num[15:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">test_pulse_num[15:0]</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="array" fp_name="/tb_control/test_pulse_height_raw">
|
||||||
|
<obj_property name="ElementShortName">test_pulse_height_raw[15:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">test_pulse_height_raw[15:0]</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="array" fp_name="/tb_control/DAC_DATA_WIDTH">
|
||||||
|
<obj_property name="ElementShortName">DAC_DATA_WIDTH[31:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">DAC_DATA_WIDTH[31:0]</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="logic" fp_name="/tb_control/dut/cfg_ack_toggle_adc">
|
||||||
|
<obj_property name="ElementShortName">cfg_ack_toggle_adc</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">cfg_ack_toggle_adc</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="logic" fp_name="/tb_control/dut/cfg_ack_toggle_dac">
|
||||||
|
<obj_property name="ElementShortName">cfg_ack_toggle_dac</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">cfg_ack_toggle_dac</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
</wave_config>
|
||||||
91
rtl/generator/README.md
Normal file
91
rtl/generator/README.md
Normal file
@ -0,0 +1,91 @@
|
|||||||
|
# Генератор
|
||||||
|
|
||||||
|
Модуль выполняет задачу формирования последовательности импульсов заданной амплитуды, длительности и периода.
|
||||||
|
Дополнительно реализован механизм синхронизации с модулем сэмплера через сигналы `sample_req` и `sample_done`, позволяющий запускать сбор данных для каждого импульса и ожидать подтверждения завершения выборки перед переходом к следующему импульсу.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## Список параметров
|
||||||
|
|
||||||
|
### DATA_WIDTH
|
||||||
|
Ширина выходных данных генератора.
|
||||||
|
|
||||||
|
### ZERO_LEVEL
|
||||||
|
Уровень сигнала в состоянии отсутствия импульса (базовый уровень сигнала).
|
||||||
|
|
||||||
|
Типовые значения:
|
||||||
|
|
||||||
|
- `8192` — середина диапазона ЦАП
|
||||||
|
- `0` — нулевой уровень
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## Список входных портов
|
||||||
|
|
||||||
|
### clk_in
|
||||||
|
Сигнал тактирования модуля.
|
||||||
|
|
||||||
|
### rst
|
||||||
|
Сброс модуля и остановка генерации.
|
||||||
|
|
||||||
|
### start
|
||||||
|
Сигнал запуска последовательности импульсов.
|
||||||
|
|
||||||
|
При его активации модуль фиксирует все входные параметры и начинает генерацию.
|
||||||
|
|
||||||
|
Повторный запуск во время активной генерации блокируется с помощью внутреннего сигнала `enable`.
|
||||||
|
|
||||||
|
### [31:0] pulse_width
|
||||||
|
Длительность активной части импульса (в тактах).
|
||||||
|
|
||||||
|
### [31:0] pulse_period
|
||||||
|
Полный период импульса (в тактах).
|
||||||
|
|
||||||
|
### [DATA_WIDTH-1:0] pulse_height
|
||||||
|
Амплитуда импульса.
|
||||||
|
|
||||||
|
### [15:0] pulse_num
|
||||||
|
Количество импульсов, которое необходимо сгенерировать.
|
||||||
|
|
||||||
|
### sample_done
|
||||||
|
Сигнал подтверждения от сэмплера о завершении выборки данных для текущего импульса.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## Список выходных портов
|
||||||
|
|
||||||
|
pulse
|
||||||
|
Выходной сигнал разрешения записи сигнала
|
||||||
|
|
||||||
|
[DATA_WIDTH-1:0] pulse_height_out
|
||||||
|
Выходное значение амплитуды сигнала.
|
||||||
|
|
||||||
|
Во время активной части импульса равно `pulse_height`, вне импульса — `ZERO_LEVEL`.
|
||||||
|
|
||||||
|
sample_req
|
||||||
|
Сигнал запроса на запуск выборки в модуле сэмплера.
|
||||||
|
|
||||||
|
Поднимается в начале каждого нового импульса и снимается после получения `sample_done`.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## Логика работы
|
||||||
|
|
||||||
|
После прихода сигнала `start` модуль:
|
||||||
|
|
||||||
|
- фиксирует входные параметры генерации
|
||||||
|
- сбрасывает внутренние счетчики
|
||||||
|
- поднимает `enable = 1`
|
||||||
|
- формирует первый `sample_req`
|
||||||
|
|
||||||
|
После этого начинается последовательная генерация импульсов.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## Симуляция
|
||||||
|
Тесты запускаются автоматически через make.
|
||||||
|
```
|
||||||
|
cd tests
|
||||||
|
make sim
|
||||||
|
```
|
||||||
|
При успешном завершении теста высвечивается "ALL PASSED".
|
||||||
@ -3,7 +3,8 @@
|
|||||||
|
|
||||||
module generator
|
module generator
|
||||||
#(
|
#(
|
||||||
parameter DATA_WIDTH = 14
|
parameter DATA_WIDTH = 14,
|
||||||
|
parameter ZERO_LEVEL = 8192 // 8192 or 0
|
||||||
)
|
)
|
||||||
(
|
(
|
||||||
input clk_in,
|
input clk_in,
|
||||||
@ -33,8 +34,8 @@ module generator
|
|||||||
|
|
||||||
always @(posedge clk_in) begin
|
always @(posedge clk_in) begin
|
||||||
if (rst) begin
|
if (rst) begin
|
||||||
pulse_height_reg <= 0;
|
pulse_height_reg <= ZERO_LEVEL;
|
||||||
pulse_height_out_reg <= '0;
|
pulse_height_out_reg <= ZERO_LEVEL;
|
||||||
pulse_width_reg <= '0;
|
pulse_width_reg <= '0;
|
||||||
pulse_period_reg <= '0;
|
pulse_period_reg <= '0;
|
||||||
pulse_num_reg <= '0;
|
pulse_num_reg <= '0;
|
||||||
@ -43,21 +44,22 @@ module generator
|
|||||||
cnt_period <= '0;
|
cnt_period <= '0;
|
||||||
sample_req <= 0;
|
sample_req <= 0;
|
||||||
end else begin
|
end else begin
|
||||||
if (start) begin
|
if (start & !enable) begin
|
||||||
enable <= 1'b1;
|
enable <= 1'b1;
|
||||||
cnt_pulse_num <= '0;
|
cnt_pulse_num <= '0;
|
||||||
cnt_period <= '0;
|
cnt_period <= '0;
|
||||||
|
|
||||||
sample_req <= 1;
|
sample_req <= 1;
|
||||||
|
|
||||||
pulse_width_reg <= pulse_width;
|
pulse_width_reg <= pulse_width;
|
||||||
pulse_period_reg <= pulse_period;
|
pulse_period_reg <= pulse_period;
|
||||||
pulse_num_reg <= pulse_num;
|
pulse_num_reg <= pulse_num;
|
||||||
pulse_height_reg <= pulse_height;
|
pulse_height_reg <= pulse_height;
|
||||||
end
|
end
|
||||||
if (enable) begin
|
if (enable) begin
|
||||||
|
|
||||||
if (!sample_req && (cnt_period == 0)) begin
|
if (!sample_req && (cnt_period == 0)) begin
|
||||||
pulse_height_out_reg <= '0;
|
pulse_height_out_reg <= ZERO_LEVEL;
|
||||||
if (sample_done) begin
|
if (sample_done) begin
|
||||||
sample_req <= 1'b0;
|
sample_req <= 1'b0;
|
||||||
end
|
end
|
||||||
@ -78,7 +80,7 @@ module generator
|
|||||||
if (cnt_period <= pulse_width_reg) begin
|
if (cnt_period <= pulse_width_reg) begin
|
||||||
pulse_height_out_reg <= pulse_height_reg;
|
pulse_height_out_reg <= pulse_height_reg;
|
||||||
end else begin
|
end else begin
|
||||||
pulse_height_out_reg <= '0;
|
pulse_height_out_reg <= ZERO_LEVEL;
|
||||||
end
|
end
|
||||||
if (cnt_period == pulse_period_reg) begin
|
if (cnt_period == pulse_period_reg) begin
|
||||||
cnt_period <= 0;
|
cnt_period <= 0;
|
||||||
|
|||||||
@ -3,6 +3,7 @@
|
|||||||
module generator_tb;
|
module generator_tb;
|
||||||
|
|
||||||
parameter DATA_WIDTH = 14;
|
parameter DATA_WIDTH = 14;
|
||||||
|
parameter ZERO_LEVEL = 8192;
|
||||||
parameter CLK_PERIOD = 16;
|
parameter CLK_PERIOD = 16;
|
||||||
|
|
||||||
logic clk;
|
logic clk;
|
||||||
@ -81,7 +82,7 @@ module generator_tb;
|
|||||||
|
|
||||||
repeat(40) @(posedge clk);
|
repeat(40) @(posedge clk);
|
||||||
|
|
||||||
pulse_width = 3;
|
pulse_width = 3;
|
||||||
pulse_period = 8;
|
pulse_period = 8;
|
||||||
pulse_num = 4;
|
pulse_num = 4;
|
||||||
pulse_height = 14'h3FF;
|
pulse_height = 14'h3FF;
|
||||||
@ -89,9 +90,17 @@ module generator_tb;
|
|||||||
|
|
||||||
repeat(1) @(posedge clk);
|
repeat(1) @(posedge clk);
|
||||||
start = 0;
|
start = 0;
|
||||||
|
|
||||||
|
repeat(5) @(posedge clk);
|
||||||
|
start = 1;
|
||||||
|
pulse_height = 14'h155;
|
||||||
|
|
||||||
|
repeat(1) @(posedge clk);
|
||||||
|
start = 0;
|
||||||
|
|
||||||
repeat(50) @(posedge clk);
|
repeat(50) @(posedge clk);
|
||||||
|
|
||||||
|
|
||||||
$display("\n=== TEST FINISHED ===");
|
$display("\n=== TEST FINISHED ===");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
|
|||||||
@ -1,23 +1,139 @@
|
|||||||
# Сэмплер
|
# Сэмплер
|
||||||
Модуль выполняет задачу сбора данных с выхода АЦП, их обработку, упаковку, и передачу дальше с помощью AXI Stream интерфейса.
|
|
||||||
|
|
||||||
## Cписок параметров
|
Модуль выполняет задачу сбора данных с выхода АЦП, их обработки, упаковки и передачи дальше с помощью AXI Stream интерфейса.
|
||||||
DATA_WIDTH - ширина входных данных, получаемых с АЦП.
|
Дополнительно реализован механизм синхронизации с внешним генератором через сигналы `sample_req` и `sample_done`, позволяющий запускать сбор строго по запросу и подтверждать завершение выборки.
|
||||||
PACK_FACTOR - количество отсчетов, собираемых в один выходной пакет.
|
|
||||||
PROCESS_MODE - режим интерпретации входного кода. 0 - прямой код, 1 - дополнительный код.
|
---
|
||||||
|
|
||||||
|
## Список параметров
|
||||||
|
|
||||||
|
DATA_WIDTH
|
||||||
|
Ширина входных данных, получаемых с АЦП.
|
||||||
|
|
||||||
|
PACK_FACTOR
|
||||||
|
Количество отсчетов, собираемых в один выходной пакет.
|
||||||
|
|
||||||
|
PROCESS_MODE
|
||||||
|
Режим интерпретации входного кода:
|
||||||
|
|
||||||
|
- `0` — прямой код
|
||||||
|
- `1` — дополнительный код
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
## Список входных портов
|
## Список входных портов
|
||||||
clk_in - сигнал тактирования выходного интерфейса.
|
|
||||||
rst - сброс модуля и остановка подачи импульсов.
|
clk_in
|
||||||
[DATA_WIDTH-1:0] data_in - входной сигнал с АЦП.
|
Сигнал тактирования выходного интерфейса.
|
||||||
out_of_range - флаг выхода значений данных за допустимый диапазон. 0 - валидны, 1 - не валидны.
|
|
||||||
|
rst
|
||||||
|
Сброс модуля и остановка работы.
|
||||||
|
|
||||||
|
[DATA_WIDTH-1:0] data_in
|
||||||
|
Входной сигнал с АЦП.
|
||||||
|
|
||||||
|
out_of_range
|
||||||
|
Флаг выхода значений данных за допустимый диапазон:
|
||||||
|
|
||||||
|
- `0` — данные валидны
|
||||||
|
- `1` — данные невалидны и игнорируются
|
||||||
|
|
||||||
|
[31:0] smp_num
|
||||||
|
Количество валидных отсчетов, которое необходимо собрать после получения запроса на выборку.
|
||||||
|
|
||||||
|
sample_req
|
||||||
|
Сигнал запроса на запуск выборки.
|
||||||
|
При его активации модуль начинает сбор данных и переходит в активное состояние (`enable = 1`).
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
## Список выходных портов
|
## Список выходных портов
|
||||||
[DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata - урезанный axis формат, выходные данные. Ширина шины считается исходя из битности данных и фактора упаковки.
|
|
||||||
m_axis_tvalid - урезанный axis формат, валидность выходных данных.
|
[DATA_WIDTH*PACK_FACTOR-1:0] m_axis_tdata
|
||||||
|
Урезанный AXI Stream формат, выходные данные.
|
||||||
|
Ширина шины определяется как произведение битности данных и фактора упаковки.
|
||||||
|
|
||||||
|
m_axis_tvalid
|
||||||
|
Урезанный AXI Stream формат, сигнал валидности выходных данных.
|
||||||
|
Формируется при готовности очередного пакета.
|
||||||
|
|
||||||
|
sample_done
|
||||||
|
Сигнал завершения выборки.
|
||||||
|
Поднимается после того, как модуль собрал количество валидных отсчетов, равное `smp_num`.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
## Логика работы
|
## Логика работы
|
||||||
На каждом такте принимаются data_in (значение АЦП) и out_of_range (флаг выхода значений данных за допустимый диапазон). Если out_of_range = 1, то данные игнорируются и не попадают во внутренний буффер. В противном случае, модуль накапливает данные во внутреннем буффере, идет его заполнение до количества данных, равное PACK_FACTOR. Когда буффер оказывается заполненным, он выдает пакет упакованных данных, сопровождая их импульсом m_axis_tvalid (готовность пакета). Если PROCESS_MODE = 1, данные выдаются в дополнительном коде, если PROCESS_MODE = 0 - в прямом.
|
|
||||||
|
На каждом такте принимаются:
|
||||||
|
|
||||||
|
- `data_in` — значение АЦП
|
||||||
|
- `out_of_range` — флаг допустимости значения
|
||||||
|
|
||||||
|
Если `out_of_range = 1`, данные считаются невалидными, игнорируются и не попадают во внутренний буфер.
|
||||||
|
|
||||||
|
Если `out_of_range = 0`, данные считаются корректными и используются для дальнейшей обработки.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
### Преобразование данных
|
||||||
|
|
||||||
|
Если `PROCESS_MODE = 1`, входные данные интерпретируются как дополнительный код и преобразуются перед упаковкой.
|
||||||
|
|
||||||
|
Если `PROCESS_MODE = 0`, данные передаются без преобразования (прямой код).
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
### Запуск выборки
|
||||||
|
|
||||||
|
Сбор данных начинается только после прихода сигнала `sample_req`.
|
||||||
|
|
||||||
|
При этом:
|
||||||
|
|
||||||
|
- фиксируется значение `smp_num`
|
||||||
|
- внутренний счетчик собранных отсчетов обнуляется
|
||||||
|
- модуль переходит в активное состояние (`enable = 1`)
|
||||||
|
|
||||||
|
Пока `enable = 1`, модуль принимает только валидные отсчеты и считает их.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
### Упаковка данных
|
||||||
|
|
||||||
|
Внутренний буфер заполняется до количества данных, равного `PACK_FACTOR`.
|
||||||
|
|
||||||
|
#### Если `PACK_FACTOR = 1`
|
||||||
|
|
||||||
|
Каждый валидный отсчет сразу формирует выходной пакет:
|
||||||
|
|
||||||
|
- данные передаются в `m_axis_tdata`
|
||||||
|
- формируется импульс `m_axis_tvalid`
|
||||||
|
|
||||||
|
#### Если `PACK_FACTOR > 1`
|
||||||
|
|
||||||
|
Данные последовательно накапливаются во внутреннем сдвиговом буфере.
|
||||||
|
|
||||||
|
Когда буфер полностью заполнен:
|
||||||
|
|
||||||
|
- формируется пакет упакованных данных
|
||||||
|
- поднимается `m_axis_tvalid`
|
||||||
|
|
||||||
|
После этого начинается сбор следующего пакета.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
### Завершение выборки
|
||||||
|
|
||||||
|
Когда количество собранных валидных отсчетов достигает значения `smp_num`:
|
||||||
|
|
||||||
|
- поднимается сигнал `sample_done`
|
||||||
|
- внутренние счетчики сбрасываются
|
||||||
|
- буфер очищается
|
||||||
|
- `enable` сбрасывается в `0`
|
||||||
|
|
||||||
|
Это означает полное завершение текущего цикла выборки.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
## Симуляция
|
## Симуляция
|
||||||
Тесты запускаются автоматически через make.
|
Тесты запускаются автоматически через make.
|
||||||
|
|||||||
@ -1 +0,0 @@
|
|||||||
# mock
|
|
||||||
20
software/README.md
Normal file
20
software/README.md
Normal file
@ -0,0 +1,20 @@
|
|||||||
|
# Software
|
||||||
|
|
||||||
|
Просто скрипт на питоне, для отправки команд через ethernet и для приема и простой визуализации данных.
|
||||||
|
|
||||||
|
## Использование
|
||||||
|
Справка:
|
||||||
|
|
||||||
|
```python3 --help```
|
||||||
|
|
||||||
|
Положительный импульс:
|
||||||
|
|
||||||
|
```python3 console.py --pulse_width 3500 --pulse_period 20000 --pulse_height 15000 --pulse_num 550 --dac-bits 14```
|
||||||
|
|
||||||
|
Отрицательный импульс:
|
||||||
|
|
||||||
|
```python3 console.py --pulse_width 15000 --pulse_period 20000 --pulse_height 1500 --pulse_num 550 --dac-bits 14```
|
||||||
|
|
||||||
|
## Ограничения
|
||||||
|
Максимальный pulse_period считается как аппаратный N_MAX * WINDOW_SIZE * adc_dac_ratio, в базовой конфигурации это 512000. Максимальный pulse_num зависит от подаваемых значений и от битности аккумулятора (по умолчанию - 32), с учетом усреднений по WINDOW_SIZE это получается что-то около 2^14 накоплений.
|
||||||
|
|
||||||
Reference in New Issue
Block a user