baulin.fa/reflectometer_fpga_project
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2 Commits
Author SHA1 Message Date
babintsev.lv 0ba25a3541 add: vrtual DAC & ADC subsystem for TB 
fix: makefile
upd: clocking wiz IP
 2026-07-10 14:15:49 +03:00
Phil 5c1866d571 chore: re-organise designs for better hierarchy 2026-05-12 13:25:44 +03:00