baulin.fa/reflectometer_fpga_project
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9b189f931f4bf81cee15067783eaefad050c7791
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10 Commits
Author SHA1 Message Date
Phil 9b189f931f rtl: update accum design 2026-04-28 11:55:46 +03:00
Phil a8a3aff498 rtl: first impl of adder+accum 2026-04-22 16:38:22 +03:00
Phil b54e69dec0 chore: add clocks for accum_fifo impl test 2026-04-21 19:48:20 +03:00
Phil 7be26d9d1a chore: update tb files 2026-04-21 19:47:56 +03:00
Phil 3dcaaf8ea5 fix: better sync for accum fifo 2026-04-21 19:47:46 +03:00
Phil dfccc01225 tests: auto tb for out_axis_fifo 2026-04-21 19:47:27 +03:00
Phil 21785aaac7 rtl: send part of out_axis_fifo 2026-04-21 17:26:02 +03:00
Phil 8e46f965df fix: incorrect fifo threshold value 2026-04-17 21:58:20 +03:00
Phil 7f9ad95e68 tests: add simple tb for accum output fifo 2026-04-17 21:51:00 +03:00
Phil 4786d2d7f6 rtl: wip accum output module, currently only with write part 2026-04-17 21:50:30 +03:00