9 Commits

Include renames

Author	SHA1	Message	Date
otroubi	806bab9520	add ram	2026-07-27 19:24:59 +03:00
otroubi	95540713e0	dma ram test	2026-07-27 19:24:47 +03:00
otroubi	ee83bcbb9e	debugging testbench	2026-07-22 22:07:03 +03:00
otroubi	8648747380	debugging a module and its wrappers	2026-07-22 22:06:44 +03:00
otroubi	e06ef3a16b	changing the addition of interfaces	2026-07-21 22:37:24 +03:00
otroubi	c121c2c103	test environment for controller and dma project	2026-07-21 22:36:55 +03:00
otroubi	56c33d2769	makefile for test project	2026-07-21 22:35:32 +03:00
otroubi	fc33aa6862	rtl: little changes	2026-07-21 14:07:44 +03:00
otroubi	490d3dcfd0	creation of project for dma tests	2026-07-20 17:29:15 +03:00