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baulin.fa/reflectometer_fpga_project
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Code Issues 4 Pull Requests Actions Packages Projects Releases Wiki Activity
201 Commits 14 Branches 0 Tags
7840e0ea7b9b11b2aad5dd5fbaa5d43ba840eed2
Commit Graph
11 Commits
Author SHA1 Message Date
Phil 9c70029f3e infra: add questa makefile 2026-07-07 17:47:03 +03:00
Phil fc36390cfe chore: clean trash 2026-05-15 16:15:00 +03:00
Phil dad163b6ac infra: update scripts to auto-upgrade ip 2026-05-08 19:04:21 +03:00
Phil 4efc2f02a9 infra: increase sim time for larger tests 2026-04-28 13:29:05 +03:00
Phil 4eb937e13f infra: make default sim longer 2026-04-21 19:46:51 +03:00
Phil eea031c6c1 fix: broken (stuck) sim 2026-04-15 18:53:49 +03:00
Phil 6bb4f1efd8 infra: sim_top auto pick if exists in sim fileset 2026-04-15 13:31:47 +03:00
Phil 7d1bfe25b4 infra: update constraints to use unified ones for board and additional for debug nodes 2026-04-14 15:39:21 +03:00
Phil c372dcd942 infra: add sim support to vivado.mk targets 2026-04-14 12:30:30 +03:00
Phil a1386fc8a4 infra: add vivado.mk target for generic builds 2026-03-31 15:08:28 +03:00
baulin.fa aa1d45fe15 infra: init project structure 2026-03-25 16:17:55 +03:00
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