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baulin.fa
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reflectometer_fpga_project
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0ba25a354143a98b058dc4f12461dc87000ad1a0
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2 Commits
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babintsev.lv
0ba25a3541
add: vrtual DAC & ADC subsystem for TB
...
fix: makefile upd: clocking wiz IP
2026-07-10 14:15:49 +03:00
babintsev.lv
64f94a90e6
add: virtual DAC (100%) and ADC (80%)
...
upd: makefile
2026-07-08 17:47:56 +03:00