|
|
0ba25a3541
|
add: vrtual DAC & ADC subsystem for TB
fix: makefile
upd: clocking wiz IP
|
2026-07-10 14:15:49 +03:00 |
|
|
|
64f94a90e6
|
add: virtual DAC (100%) and ADC (80%)
upd: makefile
|
2026-07-08 17:47:56 +03:00 |
|
|
|
7665afd50b
|
add: half-baked reflectometer TB
fix: constraints port names;
ready: reflectometer top module
|
2026-07-08 14:56:51 +03:00 |
|
|
|
c3275d5b46
|
upd: ref
|
2026-07-07 15:12:48 +03:00 |
|
|
|
906d5090cd
|
reflectometer top testbench config update
|
2026-05-26 18:30:51 +03:00 |
|
|
|
dc761f31dc
|
Add reflectometer testbench stable boilerplate with tasks
|
2026-05-22 17:07:15 +03:00 |
|
|
|
10dc60b54f
|
doc: README decoration
|
2026-05-15 16:41:18 +03:00 |
|
|
|
9efbd6586f
|
chore: generator evolution
|
2026-05-15 13:36:10 +03:00 |
|
|
|
5c1866d571
|
chore: re-organise designs for better hierarchy
|
2026-05-12 13:25:44 +03:00 |
|
