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fix: refactoring

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This commit is contained in:
babintsev.lv
2026-06-16 20:26:45 +03:00
parent c0714f271e
commit fd9280737d
2 changed files with 4 additions and 4 deletions
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4
designs/adc_dac_synchoronizer/tb_sync_top.sv
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@ -76,7 +76,7 @@ module tb_top;
forever #(CLK_DAC_PERIOD/2) clk_dac = ~clk_dac; forever #(CLK_DAC_PERIOD/2) clk_dac = ~clk_dac;
end end
// === Таски для тестипрования === // === Таски для тестирования ===
// Таска сброса DAC DUT // Таска сброса DAC DUT
task automatic reset_dut_dac( task automatic reset_dut_dac(
input int rst_duration // сколько тактов держать сброс input int rst_duration // сколько тактов держать сброс
@ -299,7 +299,7 @@ module tb_top;
); );
start_dut(1); start_dut(1);
repeat(1000) @(posedge clk_adc);
$display("[TB] ALL PASSED"); $display("[TB] ALL PASSED");
$finish; $finish;

4
rtl/generator/src/generator.sv
View File

@ -69,7 +69,7 @@ module generator
dac_out <= ZERO_LEVEL; dac_out <= ZERO_LEVEL;
cnt_pulse_period++; cnt_pulse_period++;
end end
else if (cnt_pulse_period == pulse_period_reg) begin else begin
cnt_pulse_num++; cnt_pulse_num++;
cnt_pulse_period <= 0; cnt_pulse_period <= 0;
synced <= 0; synced <= 0;
@ -77,7 +77,7 @@ module generator
end end
end end
end end
else if (cnt_pulse_num == pulse_num_reg) begin else begin
cnt_pulse_num <= 0; cnt_pulse_num <= 0;
enable <= 0; enable <= 0;
end end