From fd9280737dfde7315dcf35cbffb76e565417b29c Mon Sep 17 00:00:00 2001
From: "babintsev.lv" <lvbabintsev@edu.hse.ru>
Date: Tue, 16 Jun 2026 20:26:45 +0300
Subject: [PATCH] fix: refactoring

---
 designs/adc_dac_synchoronizer/tb_sync_top.sv | 4 ++--
 rtl/generator/src/generator.sv               | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/designs/adc_dac_synchoronizer/tb_sync_top.sv b/designs/adc_dac_synchoronizer/tb_sync_top.sv
index 94e7c18..7737d93 100644
--- a/designs/adc_dac_synchoronizer/tb_sync_top.sv
+++ b/designs/adc_dac_synchoronizer/tb_sync_top.sv
@@ -76,7 +76,7 @@ module tb_top;
         forever #(CLK_DAC_PERIOD/2) clk_dac = ~clk_dac;
     end
 
-    // === Таски для тестипрования ===
+    // === Таски для тестирования ===
     // Таска сброса DAC DUT
     task automatic reset_dut_dac(
         input int rst_duration    // сколько тактов держать сброс
@@ -299,7 +299,7 @@ module tb_top;
         );
         start_dut(1);
 
-        
+        repeat(1000) @(posedge clk_adc);
 
         $display("[TB] ALL PASSED");
         $finish;
diff --git a/rtl/generator/src/generator.sv b/rtl/generator/src/generator.sv
index 862c59e..865677a 100644
--- a/rtl/generator/src/generator.sv
+++ b/rtl/generator/src/generator.sv
@@ -69,7 +69,7 @@ module generator
                                 dac_out <= ZERO_LEVEL;
                             cnt_pulse_period++;
                         end
-                        else if (cnt_pulse_period == pulse_period_reg) begin
+                        else begin
                             cnt_pulse_num++;
                             cnt_pulse_period    <=  0;
                             synced              <=  0;
@@ -77,7 +77,7 @@ module generator
                         end
                     end
                 end
-                else if (cnt_pulse_num == pulse_num_reg) begin
+                else begin
                     cnt_pulse_num   <=  0;
                     enable          <=  0;
                 end