improved readability

rtl/controller_new/src/controller.sv

@@ -9,7 +9,9 @@ module control #(
     input  logic                       rst_soft,
 
     // adc_clk_in domain
+    // status signals
     input  logic                       finish,
+    output logic                       busy,
 
     input  logic                       accum_done,
     output logic                       accum_done_out,
@@ -18,9 +20,6 @@ module control #(
     input  logic                       cfg_bus_valid,
     input  logic                       start,
 
-    // status signals
-    output logic                       busy,
-
     // dac_clk_in domain outputs
     output logic [31:0]                dac_pulse_width,
     output logic [31:0]                dac_pulse_period,