From ed38e377a68798db3a5cbfab554fc33c8e72eb9b Mon Sep 17 00:00:00 2001 From: otroubi Date: Fri, 31 Jul 2026 12:42:29 +0300 Subject: [PATCH] improved readability --- rtl/controller_new/src/controller.sv | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/rtl/controller_new/src/controller.sv b/rtl/controller_new/src/controller.sv index b556763..ae1b7a4 100644 --- a/rtl/controller_new/src/controller.sv +++ b/rtl/controller_new/src/controller.sv @@ -9,7 +9,9 @@ module control #( input logic rst_soft, // adc_clk_in domain + // status signals input logic finish, + output logic busy, input logic accum_done, output logic accum_done_out, @@ -18,9 +20,6 @@ module control #( input logic cfg_bus_valid, input logic start, - // status signals - output logic busy, - // dac_clk_in domain outputs output logic [31:0] dac_pulse_width, output logic [31:0] dac_pulse_period, @@ -160,7 +159,7 @@ module control #( end end - // accum_done event: ADC -> cntrl via CDC + // accum_done event: ADC -> cntrl via CDC logic accum_done_meta, accum_done_sync; always_ff @(posedge ctrl_clk or posedge ctrl_rst) begin