baulin.fa/reflectometer_fpga_project
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improved readability

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otroubi
2026-07-31 12:42:29 +03:00
parent d9042042ff
commit ed38e377a6
1 changed files with 3 additions and 4 deletions
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rtl/controller_new/src/controller.sv
+3 -4
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@@ -9,7 +9,9 @@ module control #(
input logic rst_soft, input logic rst_soft,
// adc_clk_in domain // adc_clk_in domain
// status signals
input logic finish, input logic finish,
output logic busy,
input logic accum_done, input logic accum_done,
output logic accum_done_out, output logic accum_done_out,
@@ -18,9 +20,6 @@ module control #(
input logic cfg_bus_valid, input logic cfg_bus_valid,
input logic start, input logic start,
// status signals
output logic busy,
// dac_clk_in domain outputs // dac_clk_in domain outputs
output logic [31:0] dac_pulse_width, output logic [31:0] dac_pulse_width,
output logic [31:0] dac_pulse_period, output logic [31:0] dac_pulse_period,
@@ -160,7 +159,7 @@ module control #(
end end
end end
// accum_done event: ADC -> cntrl via CDC // accum_done event: ADC -> cntrl via CDC
logic accum_done_meta, accum_done_sync; logic accum_done_meta, accum_done_sync;
always_ff @(posedge ctrl_clk or posedge ctrl_rst) begin always_ff @(posedge ctrl_clk or posedge ctrl_rst) begin