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rtl: update controller to support different smp_num for adc/dac sides

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Phil
2026-05-08 15:59:20 +03:00
parent 2a928c2407
commit ecb2ed3b7f
2 changed files with 25 additions and 15 deletions
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12
rtl/controller/src/controller.sv
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@ -109,9 +109,11 @@ module control #(
// [63:32] pulse_period
// [79:64] pulse_num
// [95:80] pulse_height_raw[15:0]
// [127:96] pulse_period_ADC
//
// -------------------------------------------------------------------------
(* MARK_DEBUG="true" *) logic [95:0] cfg_bus_eth;
logic [95:0] cfg_shift_eth;
(* MARK_DEBUG="true" *) logic [127:0] cfg_bus_eth;
logic [127:0] cfg_shift_eth;
// ETH-domain parser and control
typedef enum logic [2:0] {
@ -278,10 +280,10 @@ module control #(
// little endian packing
cfg_shift_eth[cfg_byte_cnt*8 +: 8] <= s_axis_tdata;
if (cfg_byte_cnt == 4'd11) begin
if (cfg_byte_cnt == 4'd15) begin
// this must be the final payload byte
if (s_axis_tlast) begin
cfg_bus_eth <= {s_axis_tdata, cfg_shift_eth[87:0]};
cfg_bus_eth <= {s_axis_tdata, cfg_shift_eth[119:0]};
cfg_req_toggle_dac_eth <= ~cfg_req_toggle_dac_eth;
cfg_req_toggle_adc_eth <= ~cfg_req_toggle_adc_eth;
cfg_wait_dac_ack <= 1'b1;
@ -451,7 +453,7 @@ module control #(
cfg_req_sync_adc_d <= cfg_req_sync_adc;
if (cfg_req_pulse_adc) begin
adc_pulse_period <= cfg_bus_eth[63:32];
adc_pulse_period <= cfg_bus_eth[127:96];
adc_pulse_num <= cfg_bus_eth[79:64];
cfg_ack_toggle_adc <= ~cfg_ack_toggle_adc;