fix: rework wrapper for tests
This commit is contained in:
Phil
@ -16,7 +16,13 @@ module tb_controller_wrapper_axil #(
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parameter int unsigned WRITE_DESC_WIDTH = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH,
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parameter int unsigned WRITE_DESC_WIDTH = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH,
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parameter int unsigned READ_STATUS_WIDTH = TAG_WIDTH + 4,
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parameter int unsigned READ_STATUS_WIDTH = TAG_WIDTH + 4,
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parameter int unsigned WRITE_STATUS_WIDTH = LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH + 4
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parameter int unsigned WRITE_STATUS_WIDTH = LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH + 4,
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// ceil(width / 8), чтобы keep/strb не стали слишком узкими для нестандартных ширин типа 12/49/61.
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parameter int unsigned READ_DESC_KEEP_W = (READ_DESC_WIDTH + 7) / 8,
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parameter int unsigned WRITE_DESC_KEEP_W = (WRITE_DESC_WIDTH + 7) / 8,
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parameter int unsigned READ_STATUS_KEEP_W = (READ_STATUS_WIDTH + 7) / 8,
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parameter int unsigned WRITE_STATUS_KEEP_W = (WRITE_STATUS_WIDTH + 7) / 8
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)(
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)(
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input logic ctrl_clk,
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input logic ctrl_clk,
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input logic rst,
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input logic rst,
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@ -43,7 +49,31 @@ module tb_controller_wrapper_axil #(
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output logic [DATA_W-1:0] s_axil_rdata,
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output logic [DATA_W-1:0] s_axil_rdata,
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output logic [1:0] s_axil_rresp,
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output logic [1:0] s_axil_rresp,
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output logic s_axil_rvalid,
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output logic s_axil_rvalid,
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input logic s_axil_rready
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input logic s_axil_rready,
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// ---------------------------------------------------------------------------
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// Минимальный flat-view для DMA AXIS портов.
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// Наружу оставлены только tdata/tvalid/tready в старом стиле.
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// Все остальные AXIS поля внутри обёртки завязаны на безопасные значения.
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// ---------------------------------------------------------------------------
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// DUT master -> testbench: descriptor commands.
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output logic [READ_DESC_WIDTH-1:0] desc_read_cmd_out,
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output logic valid_desc_read,
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input logic ready_desc_read,
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output logic [WRITE_DESC_WIDTH-1:0] desc_write_cmd_out,
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output logic valid_desc_write,
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input logic ready_desc_write,
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// testbench -> DUT slave: status commands.
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input logic [READ_STATUS_WIDTH-1:0] status_read_cmd_in,
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input logic valid_status_read,
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output logic ready_status_read,
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input logic [WRITE_STATUS_WIDTH-1:0] status_write_cmd_in,
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input logic valid_status_write,
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output logic ready_status_write
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);
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);
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logic rst_n;
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logic rst_n;
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@ -58,6 +88,10 @@ module tb_controller_wrapper_axil #(
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logic finish;
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logic finish;
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assign finish = 1'b0;
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assign finish = 1'b0;
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// ---------------------------------------------------------------------------
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// AXI-Lite flat -> axi4l_if
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// ---------------------------------------------------------------------------
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axi4l_if #(
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axi4l_if #(
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.ADDR_W(ADDR_W),
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.ADDR_W(ADDR_W),
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.DATA_W(DATA_W),
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.DATA_W(DATA_W),
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@ -71,7 +105,7 @@ module tb_controller_wrapper_axil #(
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.ADDR_W(ADDR_W),
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.ADDR_W(ADDR_W),
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.DATA_W(DATA_W),
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.DATA_W(DATA_W),
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.USER_W(USER_W)
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.USER_W(USER_W)
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) u_flat_to_if (
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) u_axil_flat_to_if (
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.s_axil_awaddr (s_axil_awaddr),
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.s_axil_awaddr (s_axil_awaddr),
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.s_axil_awprot (s_axil_awprot),
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.s_axil_awprot (s_axil_awprot),
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.s_axil_awvalid(s_axil_awvalid),
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.s_axil_awvalid(s_axil_awvalid),
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@ -99,6 +133,150 @@ module tb_controller_wrapper_axil #(
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.m_axil(axil_bus)
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.m_axil(axil_bus)
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);
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);
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// ---------------------------------------------------------------------------
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// AXIS interfaces for the updated controller_wrapper_axil
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// ---------------------------------------------------------------------------
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axis_if #(
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.DATA_W(READ_STATUS_WIDTH),
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.KEEP_W(READ_STATUS_KEEP_W),
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.ID_W(AXIS_ID_WIDTH),
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.DEST_W(AXIS_DEST_WIDTH),
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.USER_W(AXIS_USER_WIDTH)
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) axis_status_read (
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.aclk(ctrl_clk),
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.aresetn(rst_n)
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);
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axis_if #(
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.DATA_W(WRITE_STATUS_WIDTH),
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.KEEP_W(WRITE_STATUS_KEEP_W),
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.ID_W(AXIS_ID_WIDTH),
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.DEST_W(AXIS_DEST_WIDTH),
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.USER_W(AXIS_USER_WIDTH)
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) axis_status_write (
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.aclk(ctrl_clk),
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.aresetn(rst_n)
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);
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axis_if #(
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.DATA_W(READ_DESC_WIDTH),
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.KEEP_W(READ_DESC_KEEP_W),
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.ID_W(AXIS_ID_WIDTH),
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.DEST_W(AXIS_DEST_WIDTH),
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.USER_W(AXIS_USER_WIDTH)
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) axis_desc_read (
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.aclk(ctrl_clk),
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.aresetn(rst_n)
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);
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axis_if #(
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.DATA_W(WRITE_DESC_WIDTH),
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.KEEP_W(WRITE_DESC_KEEP_W),
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.ID_W(AXIS_ID_WIDTH),
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.DEST_W(AXIS_DEST_WIDTH),
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.USER_W(AXIS_USER_WIDTH)
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) axis_desc_write (
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.aclk(ctrl_clk),
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.aresetn(rst_n)
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);
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// testbench flat status -> DUT AXIS slave ports
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axis_flat_to_if #(
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.DATA_W(READ_STATUS_WIDTH),
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.KEEP_W(READ_STATUS_KEEP_W),
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.ID_W(AXIS_ID_WIDTH),
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.DEST_W(AXIS_DEST_WIDTH),
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.USER_W(AXIS_USER_WIDTH)
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) u_status_read_flat_to_if (
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.s_axis_tdata (status_read_cmd_in),
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.s_axis_tkeep ({READ_STATUS_KEEP_W{1'b1}}),
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.s_axis_tstrb ({READ_STATUS_KEEP_W{1'b1}}),
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.s_axis_tlast (1'b1),
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.s_axis_tid ('0),
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.s_axis_tdest ('0),
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.s_axis_tuser ('0),
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.s_axis_tvalid(valid_status_read),
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.s_axis_tready(ready_status_read),
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.m_axis(axis_status_read)
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);
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axis_flat_to_if #(
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.DATA_W(WRITE_STATUS_WIDTH),
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.KEEP_W(WRITE_STATUS_KEEP_W),
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.ID_W(AXIS_ID_WIDTH),
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.DEST_W(AXIS_DEST_WIDTH),
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.USER_W(AXIS_USER_WIDTH)
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) u_status_write_flat_to_if (
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.s_axis_tdata (status_write_cmd_in),
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.s_axis_tkeep ({WRITE_STATUS_KEEP_W{1'b1}}),
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.s_axis_tstrb ({WRITE_STATUS_KEEP_W{1'b1}}),
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.s_axis_tlast (1'b1),
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.s_axis_tid ('0),
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.s_axis_tdest ('0),
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.s_axis_tuser ('0),
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.s_axis_tvalid(valid_status_write),
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.s_axis_tready(ready_status_write),
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.m_axis(axis_status_write)
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);
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// DUT AXIS master ports -> testbench flat descriptor outputs
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logic [READ_DESC_KEEP_W-1:0] unused_desc_read_tkeep;
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logic [READ_DESC_KEEP_W-1:0] unused_desc_read_tstrb;
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logic unused_desc_read_tlast;
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logic [AXIS_ID_WIDTH-1:0] unused_desc_read_tid;
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logic [AXIS_DEST_WIDTH-1:0] unused_desc_read_tdest;
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logic [AXIS_USER_WIDTH-1:0] unused_desc_read_tuser;
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axis_if_to_flat #(
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.DATA_W(READ_DESC_WIDTH),
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.KEEP_W(READ_DESC_KEEP_W),
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.ID_W(AXIS_ID_WIDTH),
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.DEST_W(AXIS_DEST_WIDTH),
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.USER_W(AXIS_USER_WIDTH)
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) u_desc_read_if_to_flat (
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.s_axis(axis_desc_read),
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.m_axis_tdata (desc_read_cmd_out),
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.m_axis_tkeep (unused_desc_read_tkeep),
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.m_axis_tstrb (unused_desc_read_tstrb),
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.m_axis_tlast (unused_desc_read_tlast),
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.m_axis_tid (unused_desc_read_tid),
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.m_axis_tdest (unused_desc_read_tdest),
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.m_axis_tuser (unused_desc_read_tuser),
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.m_axis_tvalid(valid_desc_read),
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.m_axis_tready(ready_desc_read)
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);
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logic [WRITE_DESC_KEEP_W-1:0] unused_desc_write_tkeep;
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logic [WRITE_DESC_KEEP_W-1:0] unused_desc_write_tstrb;
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logic unused_desc_write_tlast;
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logic [AXIS_ID_WIDTH-1:0] unused_desc_write_tid;
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logic [AXIS_DEST_WIDTH-1:0] unused_desc_write_tdest;
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logic [AXIS_USER_WIDTH-1:0] unused_desc_write_tuser;
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axis_if_to_flat #(
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.DATA_W(WRITE_DESC_WIDTH),
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.KEEP_W(WRITE_DESC_KEEP_W),
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.ID_W(AXIS_ID_WIDTH),
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.DEST_W(AXIS_DEST_WIDTH),
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.USER_W(AXIS_USER_WIDTH)
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) u_desc_write_if_to_flat (
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.s_axis(axis_desc_write),
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.m_axis_tdata (desc_write_cmd_out),
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.m_axis_tkeep (unused_desc_write_tkeep),
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.m_axis_tstrb (unused_desc_write_tstrb),
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.m_axis_tlast (unused_desc_write_tlast),
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.m_axis_tid (unused_desc_write_tid),
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.m_axis_tdest (unused_desc_write_tdest),
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.m_axis_tuser (unused_desc_write_tuser),
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.m_axis_tvalid(valid_desc_write),
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.m_axis_tready(ready_desc_write)
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);
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// Controller ADC/DAC outputs.
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// Controller ADC/DAC outputs.
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logic [31:0] adc_window_size;
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logic [31:0] adc_window_size;
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logic [31:0] dac_pulse_width;
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logic [31:0] dac_pulse_width;
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@ -112,30 +290,6 @@ module tb_controller_wrapper_axil #(
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logic dac_rst;
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logic dac_rst;
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logic adc_rst;
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logic adc_rst;
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// DMA side. Для базового AXI-Lite теста даём спокойные значения.
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logic ready_desc_read;
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logic ready_desc_write;
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logic ready_status_read;
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logic ready_status_write;
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logic valid_desc_read;
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logic valid_desc_write;
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logic valid_status_read;
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logic valid_status_write;
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logic [READ_STATUS_WIDTH-1:0] status_read_cmd_in;
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logic [WRITE_STATUS_WIDTH-1:0] status_write_cmd_in;
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logic [READ_DESC_WIDTH-1:0] desc_read_cmd_out;
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logic [WRITE_DESC_WIDTH-1:0] desc_write_cmd_out;
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assign ready_desc_read = 1'b1;
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assign ready_desc_write = 1'b1;
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assign valid_status_read = 1'b0;
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assign valid_status_write = 1'b0;
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assign status_read_cmd_in = '0;
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assign status_write_cmd_in = '0;
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controller_wrapper_axil #(
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controller_wrapper_axil #(
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.ADDR_W(ADDR_W),
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.ADDR_W(ADDR_W),
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.DATA_W(DATA_W),
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.DATA_W(DATA_W),
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@ -174,23 +328,11 @@ module tb_controller_wrapper_axil #(
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.dac_rst(dac_rst),
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.dac_rst(dac_rst),
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.adc_rst(adc_rst),
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.adc_rst(adc_rst),
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.ready_desc_read(ready_desc_read),
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.s_axis_status_read(axis_status_read),
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.ready_desc_write(ready_desc_write),
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.s_axis_status_write(axis_status_write),
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.ready_status_read(ready_status_read),
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.m_axis_desc_read(axis_desc_read),
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.ready_status_write(ready_status_write),
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.m_axis_desc_write(axis_desc_write)
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.valid_desc_read(valid_desc_read),
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.valid_desc_write(valid_desc_write),
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.valid_status_read(valid_status_read),
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.valid_status_write(valid_status_write),
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.status_read_cmd_in(status_read_cmd_in),
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.status_write_cmd_in(status_write_cmd_in),
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.desc_read_cmd_out(desc_read_cmd_out),
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.desc_write_cmd_out(desc_write_cmd_out)
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);
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);
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endmodule
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endmodule : tb_controller_wrapper_axil
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