From e685a6a9fc6c3532b6c9ce2e570cd15019e24834 Mon Sep 17 00:00:00 2001 From: Phil Date: Tue, 14 Jul 2026 20:07:34 +0300 Subject: [PATCH] fix: rework wrapper for tests --- .../tests/tb_controller_wrapper_axil.sv | 230 ++++++++++++++---- 1 file changed, 186 insertions(+), 44 deletions(-) diff --git a/rtl/controller/tests/tb_controller_wrapper_axil.sv b/rtl/controller/tests/tb_controller_wrapper_axil.sv index 8458e25..dd39a50 100644 --- a/rtl/controller/tests/tb_controller_wrapper_axil.sv +++ b/rtl/controller/tests/tb_controller_wrapper_axil.sv @@ -16,7 +16,13 @@ module tb_controller_wrapper_axil #( parameter int unsigned WRITE_DESC_WIDTH = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH, parameter int unsigned READ_STATUS_WIDTH = TAG_WIDTH + 4, - parameter int unsigned WRITE_STATUS_WIDTH = LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH + 4 + parameter int unsigned WRITE_STATUS_WIDTH = LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH + 4, + + // ceil(width / 8), чтобы keep/strb не стали слишком узкими для нестандартных ширин типа 12/49/61. + parameter int unsigned READ_DESC_KEEP_W = (READ_DESC_WIDTH + 7) / 8, + parameter int unsigned WRITE_DESC_KEEP_W = (WRITE_DESC_WIDTH + 7) / 8, + parameter int unsigned READ_STATUS_KEEP_W = (READ_STATUS_WIDTH + 7) / 8, + parameter int unsigned WRITE_STATUS_KEEP_W = (WRITE_STATUS_WIDTH + 7) / 8 )( input logic ctrl_clk, input logic rst, @@ -43,7 +49,31 @@ module tb_controller_wrapper_axil #( output logic [DATA_W-1:0] s_axil_rdata, output logic [1:0] s_axil_rresp, output logic s_axil_rvalid, - input logic s_axil_rready + input logic s_axil_rready, + + // --------------------------------------------------------------------------- + // Минимальный flat-view для DMA AXIS портов. + // Наружу оставлены только tdata/tvalid/tready в старом стиле. + // Все остальные AXIS поля внутри обёртки завязаны на безопасные значения. + // --------------------------------------------------------------------------- + + // DUT master -> testbench: descriptor commands. + output logic [READ_DESC_WIDTH-1:0] desc_read_cmd_out, + output logic valid_desc_read, + input logic ready_desc_read, + + output logic [WRITE_DESC_WIDTH-1:0] desc_write_cmd_out, + output logic valid_desc_write, + input logic ready_desc_write, + + // testbench -> DUT slave: status commands. + input logic [READ_STATUS_WIDTH-1:0] status_read_cmd_in, + input logic valid_status_read, + output logic ready_status_read, + + input logic [WRITE_STATUS_WIDTH-1:0] status_write_cmd_in, + input logic valid_status_write, + output logic ready_status_write ); logic rst_n; @@ -58,6 +88,10 @@ module tb_controller_wrapper_axil #( logic finish; assign finish = 1'b0; + // --------------------------------------------------------------------------- + // AXI-Lite flat -> axi4l_if + // --------------------------------------------------------------------------- + axi4l_if #( .ADDR_W(ADDR_W), .DATA_W(DATA_W), @@ -71,7 +105,7 @@ module tb_controller_wrapper_axil #( .ADDR_W(ADDR_W), .DATA_W(DATA_W), .USER_W(USER_W) - ) u_flat_to_if ( + ) u_axil_flat_to_if ( .s_axil_awaddr (s_axil_awaddr), .s_axil_awprot (s_axil_awprot), .s_axil_awvalid(s_axil_awvalid), @@ -99,6 +133,150 @@ module tb_controller_wrapper_axil #( .m_axil(axil_bus) ); + // --------------------------------------------------------------------------- + // AXIS interfaces for the updated controller_wrapper_axil + // --------------------------------------------------------------------------- + + axis_if #( + .DATA_W(READ_STATUS_WIDTH), + .KEEP_W(READ_STATUS_KEEP_W), + .ID_W(AXIS_ID_WIDTH), + .DEST_W(AXIS_DEST_WIDTH), + .USER_W(AXIS_USER_WIDTH) + ) axis_status_read ( + .aclk(ctrl_clk), + .aresetn(rst_n) + ); + + axis_if #( + .DATA_W(WRITE_STATUS_WIDTH), + .KEEP_W(WRITE_STATUS_KEEP_W), + .ID_W(AXIS_ID_WIDTH), + .DEST_W(AXIS_DEST_WIDTH), + .USER_W(AXIS_USER_WIDTH) + ) axis_status_write ( + .aclk(ctrl_clk), + .aresetn(rst_n) + ); + + axis_if #( + .DATA_W(READ_DESC_WIDTH), + .KEEP_W(READ_DESC_KEEP_W), + .ID_W(AXIS_ID_WIDTH), + .DEST_W(AXIS_DEST_WIDTH), + .USER_W(AXIS_USER_WIDTH) + ) axis_desc_read ( + .aclk(ctrl_clk), + .aresetn(rst_n) + ); + + axis_if #( + .DATA_W(WRITE_DESC_WIDTH), + .KEEP_W(WRITE_DESC_KEEP_W), + .ID_W(AXIS_ID_WIDTH), + .DEST_W(AXIS_DEST_WIDTH), + .USER_W(AXIS_USER_WIDTH) + ) axis_desc_write ( + .aclk(ctrl_clk), + .aresetn(rst_n) + ); + + // testbench flat status -> DUT AXIS slave ports + axis_flat_to_if #( + .DATA_W(READ_STATUS_WIDTH), + .KEEP_W(READ_STATUS_KEEP_W), + .ID_W(AXIS_ID_WIDTH), + .DEST_W(AXIS_DEST_WIDTH), + .USER_W(AXIS_USER_WIDTH) + ) u_status_read_flat_to_if ( + .s_axis_tdata (status_read_cmd_in), + .s_axis_tkeep ({READ_STATUS_KEEP_W{1'b1}}), + .s_axis_tstrb ({READ_STATUS_KEEP_W{1'b1}}), + .s_axis_tlast (1'b1), + .s_axis_tid ('0), + .s_axis_tdest ('0), + .s_axis_tuser ('0), + .s_axis_tvalid(valid_status_read), + .s_axis_tready(ready_status_read), + + .m_axis(axis_status_read) + ); + + axis_flat_to_if #( + .DATA_W(WRITE_STATUS_WIDTH), + .KEEP_W(WRITE_STATUS_KEEP_W), + .ID_W(AXIS_ID_WIDTH), + .DEST_W(AXIS_DEST_WIDTH), + .USER_W(AXIS_USER_WIDTH) + ) u_status_write_flat_to_if ( + .s_axis_tdata (status_write_cmd_in), + .s_axis_tkeep ({WRITE_STATUS_KEEP_W{1'b1}}), + .s_axis_tstrb ({WRITE_STATUS_KEEP_W{1'b1}}), + .s_axis_tlast (1'b1), + .s_axis_tid ('0), + .s_axis_tdest ('0), + .s_axis_tuser ('0), + .s_axis_tvalid(valid_status_write), + .s_axis_tready(ready_status_write), + + .m_axis(axis_status_write) + ); + + // DUT AXIS master ports -> testbench flat descriptor outputs + logic [READ_DESC_KEEP_W-1:0] unused_desc_read_tkeep; + logic [READ_DESC_KEEP_W-1:0] unused_desc_read_tstrb; + logic unused_desc_read_tlast; + logic [AXIS_ID_WIDTH-1:0] unused_desc_read_tid; + logic [AXIS_DEST_WIDTH-1:0] unused_desc_read_tdest; + logic [AXIS_USER_WIDTH-1:0] unused_desc_read_tuser; + + axis_if_to_flat #( + .DATA_W(READ_DESC_WIDTH), + .KEEP_W(READ_DESC_KEEP_W), + .ID_W(AXIS_ID_WIDTH), + .DEST_W(AXIS_DEST_WIDTH), + .USER_W(AXIS_USER_WIDTH) + ) u_desc_read_if_to_flat ( + .s_axis(axis_desc_read), + + .m_axis_tdata (desc_read_cmd_out), + .m_axis_tkeep (unused_desc_read_tkeep), + .m_axis_tstrb (unused_desc_read_tstrb), + .m_axis_tlast (unused_desc_read_tlast), + .m_axis_tid (unused_desc_read_tid), + .m_axis_tdest (unused_desc_read_tdest), + .m_axis_tuser (unused_desc_read_tuser), + .m_axis_tvalid(valid_desc_read), + .m_axis_tready(ready_desc_read) + ); + + logic [WRITE_DESC_KEEP_W-1:0] unused_desc_write_tkeep; + logic [WRITE_DESC_KEEP_W-1:0] unused_desc_write_tstrb; + logic unused_desc_write_tlast; + logic [AXIS_ID_WIDTH-1:0] unused_desc_write_tid; + logic [AXIS_DEST_WIDTH-1:0] unused_desc_write_tdest; + logic [AXIS_USER_WIDTH-1:0] unused_desc_write_tuser; + + axis_if_to_flat #( + .DATA_W(WRITE_DESC_WIDTH), + .KEEP_W(WRITE_DESC_KEEP_W), + .ID_W(AXIS_ID_WIDTH), + .DEST_W(AXIS_DEST_WIDTH), + .USER_W(AXIS_USER_WIDTH) + ) u_desc_write_if_to_flat ( + .s_axis(axis_desc_write), + + .m_axis_tdata (desc_write_cmd_out), + .m_axis_tkeep (unused_desc_write_tkeep), + .m_axis_tstrb (unused_desc_write_tstrb), + .m_axis_tlast (unused_desc_write_tlast), + .m_axis_tid (unused_desc_write_tid), + .m_axis_tdest (unused_desc_write_tdest), + .m_axis_tuser (unused_desc_write_tuser), + .m_axis_tvalid(valid_desc_write), + .m_axis_tready(ready_desc_write) + ); + // Controller ADC/DAC outputs. logic [31:0] adc_window_size; logic [31:0] dac_pulse_width; @@ -112,30 +290,6 @@ module tb_controller_wrapper_axil #( logic dac_rst; logic adc_rst; - // DMA side. Для базового AXI-Lite теста даём спокойные значения. - logic ready_desc_read; - logic ready_desc_write; - logic ready_status_read; - logic ready_status_write; - - logic valid_desc_read; - logic valid_desc_write; - logic valid_status_read; - logic valid_status_write; - - logic [READ_STATUS_WIDTH-1:0] status_read_cmd_in; - logic [WRITE_STATUS_WIDTH-1:0] status_write_cmd_in; - - logic [READ_DESC_WIDTH-1:0] desc_read_cmd_out; - logic [WRITE_DESC_WIDTH-1:0] desc_write_cmd_out; - - assign ready_desc_read = 1'b1; - assign ready_desc_write = 1'b1; - assign valid_status_read = 1'b0; - assign valid_status_write = 1'b0; - assign status_read_cmd_in = '0; - assign status_write_cmd_in = '0; - controller_wrapper_axil #( .ADDR_W(ADDR_W), .DATA_W(DATA_W), @@ -174,23 +328,11 @@ module tb_controller_wrapper_axil #( .dac_rst(dac_rst), .adc_rst(adc_rst), - .ready_desc_read(ready_desc_read), - .ready_desc_write(ready_desc_write), + .s_axis_status_read(axis_status_read), + .s_axis_status_write(axis_status_write), - .ready_status_read(ready_status_read), - .ready_status_write(ready_status_write), - - .valid_desc_read(valid_desc_read), - .valid_desc_write(valid_desc_write), - - .valid_status_read(valid_status_read), - .valid_status_write(valid_status_write), - - .status_read_cmd_in(status_read_cmd_in), - .status_write_cmd_in(status_write_cmd_in), - - .desc_read_cmd_out(desc_read_cmd_out), - .desc_write_cmd_out(desc_write_cmd_out) + .m_axis_desc_read(axis_desc_read), + .m_axis_desc_write(axis_desc_write) ); -endmodule +endmodule : tb_controller_wrapper_axil