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upd: new top design WIP

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babintsev.lv
2026-06-30 17:21:49 +03:00
parent 771225cd77
commit d878bac42a
2 changed files with 243 additions and 209 deletions
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149
designs/reflectometer_base/reflectometer.sv
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@ -1,8 +1,8 @@
`timescale 1 ns / 1 ns
module reflectometer_top #(
parameter int unsigned DAC_DATA_WIDTH = 14,
parameter int unsigned ADC_DATA_WIDTH = 12,
parameter DAC_DATA_WIDTH = 14,
parameter ADC_DATA_WIDTH = 12,
parameter PACK_FACTOR = 1,
parameter PROCESS_MODE = 0,
parameter ZERO_LEVEL = 8192,
@ -11,69 +11,65 @@ module reflectometer_top #(
parameter WINDOW_SIZE = 65,
parameter PACKET_SIZE = 1024
)(
input sys_clk,
input rst_n,
input clk_sys,
input rst_n,
// Output AXI-Stream for Accumulator
input clk_m_axis,
output wire [7:0] m_axis_tx_tdata,
output wire m_axis_tx_tvalid,
input wire m_axis_tx_tready,
output wire m_axis_tx_tlast,
output [3:0] led,
// Input AXI-Stream for Controller
input clk_s_axis,
input wire [7:0] s_axis_rx_tdata,
input wire s_axis_rx_tvalid,
input wire s_axis_rx_tlast,
output wire s_axis_rx_tready,
input gmii_rx_clk,
input gmii_tx_clk,
// Reflectometer status
output wire [3:0] status_leds, // System current status indicators
input wire req_ready, // MAC handshake ready
output wire send_req, // MAC handshake send
(* MARK_DEBUG="true" *) output logic [7:0] s_axis_tx_tdata,
(* MARK_DEBUG="true" *) output logic s_axis_tx_tvalid,
(* MARK_DEBUG="true" *) input logic s_axis_tx_tready,
(* MARK_DEBUG="true" *) output logic s_axis_tx_tlast,
(* MARK_DEBUG="true" *) input wire [7:0] m_axis_rx_tdata,
(* MARK_DEBUG="true" *) input wire m_axis_rx_tvalid,
(* MARK_DEBUG="true" *) input wire m_axis_rx_tlast,
(* MARK_DEBUG="true" *) output wire m_axis_rx_tready,
// axis_mac
(* MARK_DEBUG="true" *) input logic req_ready,
(* MARK_DEBUG="true" *) output logic send_req,
// DAC
output wire p2_clk,
(* MARK_DEBUG="true" *) output wire [DAC_DATA_WIDTH-1:0] p2_data,
(* MARK_DEBUG="true" *) output wire p2_wrt,
// ADC
output ch2_clk,
(* MARK_DEBUG="true" *) input [ADC_DATA_WIDTH-1:0] ch2_data,
input ch2_otr
// Generator (DAC)
output wire dac_clock,
output wire [DAC_DATA_WIDTH-1:0] dac_out,
output wire dac_wrt,
// Sampler (ADC)
output wire adc_clock,
input wire [ADC_DATA_WIDTH-1:0] adc_data,
input wire adc_otr
);
// -------------------------------------------------------------------------
// IDELAYCTRL
// -------------------------------------------------------------------------
(* IODELAY_GROUP = "rgmii_idelay_group" *)
IDELAYCTRL IDELAYCTRL_inst (
.RDY (),
.REFCLK (sys_clk),
.RST (1'b0)
);
// -------------------------------------------------------------------------
// Generated clocks for controller
// Need to create this IP in Vivado:
// input : 200 MHz
// output0: 130 MHz
// output1: 65 MHz
// ADC:
// output0: 65 Mhz 0* phase for logic
// output1: 65 MHz 180* phase for output clocking
// DAC:
// output2: 125 Mhz 0* phase for logic
// output3: 125 MHz 180* phase for output clocking
// -------------------------------------------------------------------------
wire dac_clk;
wire adc_clk;
wire clk_wiz_locked;
wire clk_adc, clk_adc_180;
wire clk_dac, clk_dac_180;
wire locked;
clk_wiz_ctrl_inst clk_wiz_ctrl_inst (
.clk_in1 (sys_clk),
.reset (~rst_n),
.clk_out1 (dac_clk), // 130 MHz
.clk_out2 (adc_clk), // 65 MHz
.locked (clk_wiz_locked)
clk_wiz_ctrl_inst clk_wiz_inst
(
// Clock out ports
.clk_adc_65(clk_adc),
.clk_adc_65_180(clk_adc_180),
.clk_dac_125(clk_dac),
.clk_dac_125_180(clk_dac_180),
// Status and control signals
.resetn(rst_n),
.locked(locked),
// Clock in ports
.clk_sys(clk_sys)
);
// -------------------------------------------------------------------------
@ -87,24 +83,23 @@ module reflectometer_top #(
// Controller reset
// Use both external reset and clk_wiz lock
// -------------------------------------------------------------------------
wire ctrl_rst_n = rst_n & clk_wiz_locked;
wire rst_n_ctrl = rst_n & locked;
(* MARK_DEBUG="true" *) logic finish;
logic finish;
// Controller outputs to debug
(* MARK_DEBUG="true" *) wire [31:0] dac_pulse_width;
(* MARK_DEBUG="true" *) wire [31:0] dac_pulse_period;
(* MARK_DEBUG="true" *) wire [DAC_DATA_WIDTH-1:0] dac_pulse_height;
(* MARK_DEBUG="true" *) wire [15:0] dac_pulse_num;
wire [31:0] dac_pulse_width;
wire [31:0] dac_pulse_period;
wire [DAC_DATA_WIDTH-1:0] dac_pulse_height;
wire [15:0] dac_pulse_num;
(* MARK_DEBUG="true" *) wire [31:0] adc_pulse_period;
(* MARK_DEBUG="true" *) wire [15:0] adc_pulse_num;
wire [31:0] adc_pulse_period;
wire [15:0] adc_pulse_num;
(* MARK_DEBUG="true" *) wire dac_start;
(* MARK_DEBUG="true" *) wire adc_start;
(* MARK_DEBUG="true" *) wire dac_rst;
(* MARK_DEBUG="true" *) wire adc_rst;
wire dac_start;
wire adc_start;
wire dac_rst;
wire adc_rst;
// -------------------------------------------------------------------------
@ -145,15 +140,15 @@ module reflectometer_top #(
// DAC
// -------------------------------------------------------------------------
(* MARK_DEBUG="true" *) logic sample_req;
(* MARK_DEBUG="true" *) logic sample_req_sync1;
(* MARK_DEBUG="true" *) logic sample_req_sync2;
(* MARK_DEBUG="true" *) logic sample_req_sync3;
logic sample_req;
logic sample_req_sync1;
logic sample_req_sync2;
logic sample_req_sync3;
(* MARK_DEBUG="true" *) logic sample_done;
(* MARK_DEBUG="true" *) logic sample_done_sync1;
(* MARK_DEBUG="true" *) logic sample_done_sync2;
(* MARK_DEBUG="true" *) logic sample_done_sync3;
logic sample_done;
logic sample_done_sync1;
logic sample_done_sync2;
logic sample_done_sync3;
//------------------------------------------------------------
// DAC -> ADC CDC
@ -254,8 +249,8 @@ module reflectometer_top #(
// ADC
// -------------------------------------------------------------------------
(* MARK_DEBUG="true" *) logic [ADC_DATA_WIDTH*PACK_FACTOR-1:0] accum_m_axis_tdata;
(* MARK_DEBUG="true" *) logic acum_m_axis_tvalid;
logic [ADC_DATA_WIDTH*PACK_FACTOR-1:0] accum_m_axis_tdata;
logic acum_m_axis_tvalid;
sampler
#(