315 lines
9.2 KiB
Systemverilog
315 lines
9.2 KiB
Systemverilog
`timescale 1 ns / 1 ns
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module reflectometer_top #(
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parameter DAC_DATA_WIDTH = 14,
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parameter ADC_DATA_WIDTH = 12,
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parameter PACK_FACTOR = 1,
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parameter PROCESS_MODE = 0,
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parameter ZERO_LEVEL = 8192,
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parameter ACCUM_WIDTH = 32,
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parameter N_MAX = 4096,
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parameter WINDOW_SIZE = 65,
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parameter PACKET_SIZE = 1024
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)(
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input clk_sys,
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input rst_n,
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// Output AXI-Stream for Accumulator
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input clk_m_axis,
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output wire [7:0] m_axis_tx_tdata,
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output wire m_axis_tx_tvalid,
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input wire m_axis_tx_tready,
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output wire m_axis_tx_tlast,
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// Input AXI-Stream for Controller
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input clk_s_axis,
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input wire [7:0] s_axis_rx_tdata,
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input wire s_axis_rx_tvalid,
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input wire s_axis_rx_tlast,
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output wire s_axis_rx_tready,
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// Reflectometer status
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output wire [3:0] status_leds, // System current status indicators
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input wire req_ready, // MAC handshake ready
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output wire send_req, // MAC handshake send
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// Generator (DAC)
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output wire dac_clock,
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output wire [DAC_DATA_WIDTH-1:0] dac_out,
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output wire dac_wrt,
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// Sampler (ADC)
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output wire adc_clock,
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input wire [ADC_DATA_WIDTH-1:0] adc_data,
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input wire adc_otr
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);
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// -------------------------------------------------------------------------
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// Generated clocks for controller
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// Need to create this IP in Vivado:
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// input : 200 MHz
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// ADC:
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// output0: 65 Mhz 0* phase for logic
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// output1: 65 MHz 180* phase for output clocking
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// DAC:
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// output2: 125 Mhz 0* phase for logic
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// output3: 125 MHz 180* phase for output clocking
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// -------------------------------------------------------------------------
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wire clk_adc, clk_adc_180;
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wire clk_dac, clk_dac_180;
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wire locked;
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clk_wiz_ctrl_inst clk_wiz_inst
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(
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// Clock out ports
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.clk_adc_65(clk_adc),
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.clk_adc_65_180(clk_adc_180),
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.clk_dac_125(clk_dac),
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.clk_dac_125_180(clk_dac_180),
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// Status and control signals
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.resetn(rst_n),
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.locked(locked),
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// Clock in ports
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.clk_sys(clk_sys)
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);
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// -------------------------------------------------------------------------
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// axis_mac interface
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// RX stream from Ethernet goes into controller
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// TX stream is unused for now
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// -------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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// Controller reset
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// Use both external reset and clk_wiz lock
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// -------------------------------------------------------------------------
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wire rst_n_ctrl = rst_n & locked;
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logic finish;
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// Controller outputs to debug
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wire [31:0] dac_pulse_width;
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wire [31:0] dac_pulse_period;
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wire [DAC_DATA_WIDTH-1:0] dac_pulse_height;
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wire [15:0] dac_pulse_num;
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wire [31:0] adc_pulse_period;
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wire [15:0] adc_pulse_num;
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wire dac_start;
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wire adc_start;
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wire dac_rst;
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wire adc_rst;
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// -------------------------------------------------------------------------
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// Controller
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// ETH domain = gmii_rx_clk, because RX AXI master comes from axis_mac RX side
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// -------------------------------------------------------------------------
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control #(
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.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
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) udp_ctrl_inst (
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.eth_clk_in (gmii_rx_clk),
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.dac_clk_in (dac_clk),
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.adc_clk_in (adc_clk),
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.rst_n (ctrl_rst_n),
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.s_axis_tdata (m_axis_rx_tdata),
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.s_axis_tvalid (m_axis_rx_tvalid),
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.s_axis_tready (m_axis_rx_tready),
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.s_axis_tlast (m_axis_rx_tlast),
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.finish (finish),
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.dac_pulse_width (dac_pulse_width),
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.dac_pulse_period (dac_pulse_period),
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.dac_pulse_height (dac_pulse_height),
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.dac_pulse_num (dac_pulse_num),
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.adc_pulse_period (adc_pulse_period),
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.adc_pulse_num (adc_pulse_num),
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.dac_start (dac_start),
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.adc_start (adc_start),
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.dac_rst (dac_rst),
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.adc_rst (adc_rst)
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);
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// -------------------------------------------------------------------------
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// DAC
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// -------------------------------------------------------------------------
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logic sample_req;
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logic sample_req_sync1;
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logic sample_req_sync2;
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logic sample_req_sync3;
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logic sample_done;
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logic sample_done_sync1;
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logic sample_done_sync2;
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logic sample_done_sync3;
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//------------------------------------------------------------
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// DAC -> ADC CDC
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//------------------------------------------------------------
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always_ff @(posedge adc_clk or posedge adc_rst) begin
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if (adc_rst) begin
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sample_req <= 1'b0;
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sample_req_sync2 <= 1'b0;
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sample_req_sync3 <= 1'b0;
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end
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else begin
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sample_req_sync2 <= sample_req_sync1;
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sample_req_sync3 <= sample_req_sync2;
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sample_req <= sample_req_sync3;
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end
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end
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//------------------------------------------------------------
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// ADC -> DAC CDC
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//------------------------------------------------------------
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always_ff @(posedge dac_clk or posedge dac_rst) begin
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if (dac_rst) begin
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sample_done <= 1'b0;
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sample_done_sync2 <= 1'b0;
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sample_done_sync3 <= 1'b0;
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end
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else begin
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sample_done_sync2 <= sample_done_sync1;
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sample_done_sync3 <= sample_done_sync2;
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sample_done <= sample_done_sync3;
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end
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end
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//------------------------------------------------------------
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// Generator
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//------------------------------------------------------------
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generator #(
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.DATA_WIDTH(DAC_DATA_WIDTH),
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.ZERO_LEVEL(ZERO_LEVEL)
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) generator_inst (
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.clk_in(dac_clk),
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.rst(dac_rst),
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.start(dac_start),
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.pulse_width(dac_pulse_width),
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.pulse_period(dac_pulse_period),
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.pulse_height(dac_pulse_height),
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.pulse_num(dac_pulse_num),
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.pulse(p2_wrt),
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.pulse_height_out(p2_data),
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.sample_done(sample_done),
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.sample_req(sample_req_sync1)
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);
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wire ch2_clk_oddr;
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ODDR #(
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.DDR_CLK_EDGE("SAME_EDGE"),
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.INIT(1'b0),
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.SRTYPE("SYNC")
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) ODDR_ch2_clk (
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.Q (ch2_clk_oddr),
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.C (adc_clk),
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.CE(1'b1),
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.D1(1'b1),
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.D2(1'b0),
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.R (1'b0),
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.S (1'b0)
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);
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OBUF OBUF_ch2_clk (
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.I(ch2_clk_oddr),
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.O(ch2_clk)
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);
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wire p2_clk_oddr;
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ODDR #(
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.DDR_CLK_EDGE("SAME_EDGE"),
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.INIT(1'b0),
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.SRTYPE("SYNC")
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) ODDR_p2_clk (
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.Q (p2_clk_oddr),
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.C (dac_clk),
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.CE(1'b1),
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.D1(1'b1),
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.D2(1'b0),
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.R (1'b0),
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.S (1'b0)
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);
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OBUF OBUF_p2_clk (
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.I(p2_clk_oddr),
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.O(p2_clk)
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);
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// -------------------------------------------------------------------------
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// ADC
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// -------------------------------------------------------------------------
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logic [ADC_DATA_WIDTH*PACK_FACTOR-1:0] accum_m_axis_tdata;
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logic acum_m_axis_tvalid;
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sampler
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#(
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.DATA_WIDTH(ADC_DATA_WIDTH),
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.PACK_FACTOR(PACK_FACTOR),
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.PROCESS_MODE(PROCESS_MODE)
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)
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sampler_dut
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(
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.clk_in(adc_clk),
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.rst(adc_rst),
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.data_in(ch2_data),
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.out_of_range(ch2_otr),
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.m_axis_tdata(accum_m_axis_tdata),
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.m_axis_tvalid(acum_m_axis_tvalid),
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.smp_num(adc_pulse_period),
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.sample_req(sample_req),
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.sample_done(sample_done_sync1)
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);
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// -------------------------------------------------------------------------
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// Accumulator
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// -------------------------------------------------------------------------
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accumulator_top
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#(
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.DATA_WIDTH(ADC_DATA_WIDTH),
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.ACCUM_WIDTH(ACCUM_WIDTH),
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.N_MAX(N_MAX),
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.WINDOW_SIZE(WINDOW_SIZE),
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.PACKET_SIZE(PACKET_SIZE)
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)
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accumulator_top_dut
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(
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.clk_in(adc_clk),
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.rst(adc_rst),
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.s_axis_tdata(accum_m_axis_tdata),
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.s_axis_tvalid(acum_m_axis_tvalid),
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.start(adc_start),
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.smp_num(adc_pulse_period),
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.seq_num(adc_pulse_num),
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.eth_clk_in(gmii_tx_clk),
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.req_ready(req_ready),
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.send_req(send_req),
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.m_axis_tdata(s_axis_tx_tdata),
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.m_axis_tvalid(s_axis_tx_tvalid),
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.m_axis_tready(s_axis_tx_tready),
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.m_axis_tlast(s_axis_tx_tlast),
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.finish(finish)
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);
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// -------------------------------------------------------------------------
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// Simple LED status
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// -------------------------------------------------------------------------
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assign led[0] = clk_wiz_locked;
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assign led[1] = m_axis_rx_tvalid;
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assign led[2] = dac_start;
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endmodule |