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rtl: sampler synchronization modification

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otroubi
2026-06-10 13:10:50 +03:00
parent f670df9b54
commit cf2985813a
1 changed files with 31 additions and 16 deletions
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47
rtl/sampler/src/sampler.sv
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@ -21,7 +21,7 @@ module sampler
(* MARK_DEBUG="true" *) logic [DATA_WIDTH-1:0] data_converted; (* MARK_DEBUG="true" *) logic [DATA_WIDTH-1:0] data_converted;
(* MARK_DEBUG="true" *) logic out_of_range_reg; (* MARK_DEBUG="true" *) logic out_of_range_reg;
(* MARK_DEBUG="true" *) logic [31:0] smp_num_reg, cnt_smp_num; (* MARK_DEBUG="true" *) logic [31:0] smp_num_reg, cnt_smp_num;
(* MARK_DEBUG="true" *) logic enable, enable_d; (* MARK_DEBUG="true" *) logic enable;
generate generate
if (PROCESS_MODE) begin if (PROCESS_MODE) begin
@ -54,7 +54,7 @@ module sampler
endgenerate endgenerate
(* MARK_DEBUG="true" *) logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer; (* MARK_DEBUG="true" *) logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
(* MARK_DEBUG="true" *) logic buffer_ready; (* MARK_DEBUG="true" *) logic buffer_ready, wait_sync;
logic [$clog2(PACK_FACTOR):0] cnt; logic [$clog2(PACK_FACTOR):0] cnt;
@ -68,19 +68,26 @@ module sampler
smp_num_reg <= '0; smp_num_reg <= '0;
enable <= 0; enable <= 0;
request <= 0; request <= 0;
wait_sync <= 0;
end end
else begin else begin
buffer_ready <= 0; buffer_ready <= 0;
enable_d <= enable;
if (!enable) begin if (!enable) begin
if (request && done) begin if (!wait_sync) begin
enable <= 1; request <= 1'b0;
request <= 0; if (done) begin
cnt_smp_num <= 0; wait_sync <= 1'b1;
smp_num_reg <= smp_num; request <= 1'b1;
end
end else begin end else begin
request <= 1; if (!done) begin
enable <= 1'b1;
request <= 1'b0;
wait_sync <= 1'b0;
cnt_smp_num <= 0;
smp_num_reg <= smp_num;
end end
end
end else begin end else begin
if (!out_of_range_reg) begin if (!out_of_range_reg) begin
if (cnt_smp_num != smp_num_reg) begin if (cnt_smp_num != smp_num_reg) begin
@ -110,14 +117,22 @@ module sampler
end end
else begin else begin
buffer_ready <= 0; buffer_ready <= 0;
if (!enable) begin if (!enable) begin
if (!request) request <= 1; if (!wait_sync) begin
if (request && done) begin request <= 1'b0;
enable <= 1; if (done) begin
request <= 0; wait_sync <= 1'b1;
cnt_smp_num <= 0; request <= 1'b1;
smp_num_reg <= smp_num; end
end else begin
if (!done) begin
enable <= 1'b1;
request <= 1'b0;
wait_sync <= 1'b0;
cnt_smp_num <= 0;
smp_num_reg <= smp_num;
end end
end
end else begin end else begin
if (!out_of_range_reg) begin if (!out_of_range_reg) begin
if (cnt_smp_num < smp_num_reg) begin if (cnt_smp_num < smp_num_reg) begin