diff --git a/rtl/sampler/src/sampler.sv b/rtl/sampler/src/sampler.sv
index f2e99ef..393b187 100644
--- a/rtl/sampler/src/sampler.sv
+++ b/rtl/sampler/src/sampler.sv
@@ -21,7 +21,7 @@ module sampler
    (* MARK_DEBUG="true" *) logic [DATA_WIDTH-1:0] data_converted;
    (* MARK_DEBUG="true" *) logic out_of_range_reg;
     (* MARK_DEBUG="true" *) logic [31:0] smp_num_reg, cnt_smp_num;
-   (* MARK_DEBUG="true" *) logic enable, enable_d;
+   (* MARK_DEBUG="true" *) logic enable;
     
     generate
        if (PROCESS_MODE) begin 
@@ -54,7 +54,7 @@ module sampler
     endgenerate
          
   (* MARK_DEBUG="true" *)  logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
-  (* MARK_DEBUG="true" *)  logic buffer_ready;
+  (* MARK_DEBUG="true" *)  logic buffer_ready, wait_sync;
 
     logic [$clog2(PACK_FACTOR):0] cnt;
     
@@ -68,19 +68,26 @@ module sampler
                 smp_num_reg <= '0;
                 enable <= 0;
                 request <= 0;
+                wait_sync <= 0;
             end
             else begin
                 buffer_ready <= 0;
-                enable_d <= enable;
                 if (!enable) begin
-                    if (request && done) begin
-                        enable  <= 1;
-                        request <= 0;
-                        cnt_smp_num <= 0;
-                        smp_num_reg <= smp_num;
+                    if (!wait_sync) begin
+                        request <= 1'b0;
+                        if (done) begin
+                            wait_sync <= 1'b1;
+                            request   <= 1'b1;
+                        end
                     end else begin
-                        request <= 1;
+                         if (!done) begin
+                            enable      <= 1'b1;
+                            request     <= 1'b0;
+                            wait_sync   <= 1'b0;
+                            cnt_smp_num <= 0;
+                            smp_num_reg <= smp_num;
                     end
+                 end
                 end else begin
                     if (!out_of_range_reg) begin
                         if (cnt_smp_num != smp_num_reg) begin
@@ -110,14 +117,22 @@ module sampler
             end
             else begin
                 buffer_ready <= 0;
-                if (!enable) begin
-                    if (!request) request <= 1;
-                    if (request && done) begin
-                        enable      <= 1;
-                        request <= 0;
-                        cnt_smp_num <= 0;
-                        smp_num_reg <= smp_num;
+                 if (!enable) begin
+                    if (!wait_sync) begin
+                        request <= 1'b0;
+                        if (done) begin
+                            wait_sync <= 1'b1;
+                            request   <= 1'b1;
+                        end
+                    end else begin
+                         if (!done) begin
+                            enable      <= 1'b1;
+                            request     <= 1'b0;
+                            wait_sync   <= 1'b0;
+                            cnt_smp_num <= 0;
+                            smp_num_reg <= smp_num;
                     end
+                 end
                 end else begin
                     if (!out_of_range_reg) begin
                         if (cnt_smp_num < smp_num_reg) begin