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fix: controller reg map invalid mapping

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Phil
2026-07-14 17:43:47 +03:00
parent 691e69693a
commit cec4c84fd9
2 changed files with 45 additions and 65 deletions
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6
rtl/controller/src/axi4l_reg_map_controller.sv
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@ -52,7 +52,7 @@ module axi4l_reg_map_controller #(
input logic [7:0] error_code_i input logic [7:0] error_code_i
); );
import axi4l_reg_map_controller_pkg::*; import axi4l_reg_map_controller_pkg::*;
localparam int unsigned N_REGS = AXI4L_REG_MAP_EXAMPLE_N_REGS; localparam int unsigned N_REGS = CTRL_REG_MAP_N_REGS;
logic [N_REGS-1:0][31:0] reg_i; logic [N_REGS-1:0][31:0] reg_i;
logic [N_REGS-1:0][31:0] reg_o; logic [N_REGS-1:0][31:0] reg_o;
@ -63,8 +63,8 @@ module axi4l_reg_map_controller #(
.DATA_W (DATA_W), .DATA_W (DATA_W),
.USER_W (USER_W), .USER_W (USER_W),
.N_REGS (N_REGS), .N_REGS (N_REGS),
.REG_MODE (AXI4L_REG_MAP_EXAMPLE_REG_MODE), .REG_MODE (CTRL_REG_MAP_REG_MODE),
.REG_RST (AXI4L_REG_MAP_EXAMPLE_REG_RST) .REG_RST (CTRL_REG_MAP_REG_RST)
) u_reg_map ( ) u_reg_map (
.clk (clk), .clk (clk),
.rst_n (rst_n), .rst_n (rst_n),

104
rtl/controller/src/axi4l_reg_map_controller_pkg.sv
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@ -1,6 +1,6 @@
package axi4l_reg_map_controller_pkg; package axi4l_reg_map_controller_pkg;
localparam int unsigned AXI4L_REG_MAP_EXAMPLE_N_REGS = 17; localparam int unsigned CTRL_REG_MAP_N_REGS = 17;
/* /*
dac adc configuration registers dac adc configuration registers
@ -39,74 +39,54 @@ AXI write descriptor input and AXI write descriptor status output configuration
localparam logic [2:0] REG_BIT_RW = 3'd2; localparam logic [2:0] REG_BIT_RW = 3'd2;
localparam logic [2:0] REG_BIT_W1S = 3'd3; localparam logic [2:0] REG_BIT_W1S = 3'd3;
localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0][2:0] AXI4L_REG_MAP_EXAMPLE_REG_MODE = '{ localparam logic [CTRL_REG_MAP_N_REGS-1:0][31:0][2:0] CTRL_REG_MAP_REG_MODE = '{
// REG_CONTROL default: '{default: REG_BIT_RSVD},
'{
0 : REG_BIT_W1S,
1 : REG_BIT_W1S,
2 : REG_BIT_W1S,
3 : REG_BIT_W1S,
4 : REG_BIT_W1S,
5 : REG_BIT_W1S,
6 : REG_BIT_W1S,
default: REG_BIT_RSVD
},
// REG_STATUS REG_CONTROL: '{
'{ 0 : REG_BIT_W1S,
0 : REG_BIT_RO, 1 : REG_BIT_RO, 2 : REG_BIT_RO, 3 : REG_BIT_RO, 1 : REG_BIT_W1S,
4 : REG_BIT_RO, 5 : REG_BIT_RO, 6 : REG_BIT_RO, 7 : REG_BIT_RO, 2 : REG_BIT_W1S,
8 : REG_BIT_RO, 3 : REG_BIT_W1S,
default: REG_BIT_RSVD 4 : REG_BIT_W1S,
}, 5 : REG_BIT_W1S,
6 : REG_BIT_W1S,
default: REG_BIT_RSVD
},
// REG_DAC_WIDTH REG_STATUS: '{
'{default: REG_BIT_RW}, 0 : REG_BIT_RO,
1 : REG_BIT_RO,
2 : REG_BIT_RO,
3 : REG_BIT_RO,
4 : REG_BIT_RO,
5 : REG_BIT_RO,
6 : REG_BIT_RO,
7 : REG_BIT_RO,
8 : REG_BIT_RO,
default: REG_BIT_RSVD
},
// REG_DAC_PERIOD REG_DAC_WIDTH: '{default: REG_BIT_RW},
'{default: REG_BIT_RW}, REG_DAC_PERIOD: '{default: REG_BIT_RW},
REG_DAC_PULSE_NUM: '{default: REG_BIT_RW},
REG_DAC_PULSE_HEIGHT: '{default: REG_BIT_RW},
REG_ADC_PERIOD: '{default: REG_BIT_RW},
REG_WINDOW_SIZE: '{default: REG_BIT_RW},
// REG_DAC_PULSE_NUM REG_ERROR: '{default: REG_BIT_RO},
'{default: REG_BIT_RW},
// REG_DAC_PULSE_HEIGHT REG_DESC_READ_ADDR: '{default: REG_BIT_RW},
'{default: REG_BIT_RW}, REG_DESC_READ_LEN: '{default: REG_BIT_RW},
REG_DESC_READ_CONFIG: '{default: REG_BIT_RW},
REG_READ_STATUS: '{default: REG_BIT_RO},
// REG_ADC_PERIOD REG_DESC_WRITE_ADDR: '{default: REG_BIT_RW},
'{default: REG_BIT_RW}, REG_DESC_WRITE_LEN_AND_TAG: '{default: REG_BIT_RW},
REG_STATUS_WRITE_LEN: '{default: REG_BIT_RO},
REG_STATUS_WRITE_CONFIG: '{default: REG_BIT_RO}
};
// REG_WINDOW_SIZE localparam logic [CTRL_REG_MAP_N_REGS-1:0][31:0] CTRL_REG_MAP_REG_RST = '{
'{default: REG_BIT_RW},
// REG_ERROR
'{default: REG_BIT_RO},
// REG_DESC_READ_ADDR
'{default: REG_BIT_RW},
// REG_DESC_READ_LEN
'{default: REG_BIT_RW},
// REG_DESC_READ_CONFIG
'{default: REG_BIT_RW},
// REG_READ_STATUS
'{default: REG_BIT_RO},
// REG_DESC_WRITE_ADDR
'{default: REG_BIT_RW},
// REG_DESC_WRITE_LEN_AND_TAG
'{default: REG_BIT_RW},
// REG_STATUS_WRITE_LEN
'{default: REG_BIT_RO},
// REG_STATUS_WRITE_CONFIG
'{default: REG_BIT_RO}
};
localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0] AXI4L_REG_MAP_EXAMPLE_REG_RST = '{
32'h0000_0000, 32'h0000_0000,
32'h0000_0000, 32'h0000_0000,
32'h0000_0000, 32'h0000_0000,