From cec4c84fd9db5e311d49b3dc825c72924156324c Mon Sep 17 00:00:00 2001 From: Phil Date: Tue, 14 Jul 2026 17:43:47 +0300 Subject: [PATCH] fix: controller reg map invalid mapping --- .../src/axi4l_reg_map_controller.sv | 6 +- .../src/axi4l_reg_map_controller_pkg.sv | 104 +++++++----------- 2 files changed, 45 insertions(+), 65 deletions(-) diff --git a/rtl/controller/src/axi4l_reg_map_controller.sv b/rtl/controller/src/axi4l_reg_map_controller.sv index 24a42e3..7600019 100644 --- a/rtl/controller/src/axi4l_reg_map_controller.sv +++ b/rtl/controller/src/axi4l_reg_map_controller.sv @@ -52,7 +52,7 @@ module axi4l_reg_map_controller #( input logic [7:0] error_code_i ); import axi4l_reg_map_controller_pkg::*; - localparam int unsigned N_REGS = AXI4L_REG_MAP_EXAMPLE_N_REGS; + localparam int unsigned N_REGS = CTRL_REG_MAP_N_REGS; logic [N_REGS-1:0][31:0] reg_i; logic [N_REGS-1:0][31:0] reg_o; @@ -63,8 +63,8 @@ module axi4l_reg_map_controller #( .DATA_W (DATA_W), .USER_W (USER_W), .N_REGS (N_REGS), - .REG_MODE (AXI4L_REG_MAP_EXAMPLE_REG_MODE), - .REG_RST (AXI4L_REG_MAP_EXAMPLE_REG_RST) + .REG_MODE (CTRL_REG_MAP_REG_MODE), + .REG_RST (CTRL_REG_MAP_REG_RST) ) u_reg_map ( .clk (clk), .rst_n (rst_n), diff --git a/rtl/controller/src/axi4l_reg_map_controller_pkg.sv b/rtl/controller/src/axi4l_reg_map_controller_pkg.sv index 74b1656..89a593e 100644 --- a/rtl/controller/src/axi4l_reg_map_controller_pkg.sv +++ b/rtl/controller/src/axi4l_reg_map_controller_pkg.sv @@ -1,6 +1,6 @@ package axi4l_reg_map_controller_pkg; - localparam int unsigned AXI4L_REG_MAP_EXAMPLE_N_REGS = 17; + localparam int unsigned CTRL_REG_MAP_N_REGS = 17; /* dac adc configuration registers @@ -39,74 +39,54 @@ AXI write descriptor input and AXI write descriptor status output configuration localparam logic [2:0] REG_BIT_RW = 3'd2; localparam logic [2:0] REG_BIT_W1S = 3'd3; - localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0][2:0] AXI4L_REG_MAP_EXAMPLE_REG_MODE = '{ - // REG_CONTROL - '{ - 0 : REG_BIT_W1S, - 1 : REG_BIT_W1S, - 2 : REG_BIT_W1S, - 3 : REG_BIT_W1S, - 4 : REG_BIT_W1S, - 5 : REG_BIT_W1S, - 6 : REG_BIT_W1S, - default: REG_BIT_RSVD - }, + localparam logic [CTRL_REG_MAP_N_REGS-1:0][31:0][2:0] CTRL_REG_MAP_REG_MODE = '{ + default: '{default: REG_BIT_RSVD}, - // REG_STATUS - '{ - 0 : REG_BIT_RO, 1 : REG_BIT_RO, 2 : REG_BIT_RO, 3 : REG_BIT_RO, - 4 : REG_BIT_RO, 5 : REG_BIT_RO, 6 : REG_BIT_RO, 7 : REG_BIT_RO, - 8 : REG_BIT_RO, - default: REG_BIT_RSVD - }, + REG_CONTROL: '{ + 0 : REG_BIT_W1S, + 1 : REG_BIT_W1S, + 2 : REG_BIT_W1S, + 3 : REG_BIT_W1S, + 4 : REG_BIT_W1S, + 5 : REG_BIT_W1S, + 6 : REG_BIT_W1S, + default: REG_BIT_RSVD + }, - // REG_DAC_WIDTH - '{default: REG_BIT_RW}, + REG_STATUS: '{ + 0 : REG_BIT_RO, + 1 : REG_BIT_RO, + 2 : REG_BIT_RO, + 3 : REG_BIT_RO, + 4 : REG_BIT_RO, + 5 : REG_BIT_RO, + 6 : REG_BIT_RO, + 7 : REG_BIT_RO, + 8 : REG_BIT_RO, + default: REG_BIT_RSVD + }, - // REG_DAC_PERIOD - '{default: REG_BIT_RW}, + REG_DAC_WIDTH: '{default: REG_BIT_RW}, + REG_DAC_PERIOD: '{default: REG_BIT_RW}, + REG_DAC_PULSE_NUM: '{default: REG_BIT_RW}, + REG_DAC_PULSE_HEIGHT: '{default: REG_BIT_RW}, + REG_ADC_PERIOD: '{default: REG_BIT_RW}, + REG_WINDOW_SIZE: '{default: REG_BIT_RW}, - // REG_DAC_PULSE_NUM - '{default: REG_BIT_RW}, + REG_ERROR: '{default: REG_BIT_RO}, - // REG_DAC_PULSE_HEIGHT - '{default: REG_BIT_RW}, + REG_DESC_READ_ADDR: '{default: REG_BIT_RW}, + REG_DESC_READ_LEN: '{default: REG_BIT_RW}, + REG_DESC_READ_CONFIG: '{default: REG_BIT_RW}, + REG_READ_STATUS: '{default: REG_BIT_RO}, - // REG_ADC_PERIOD - '{default: REG_BIT_RW}, + REG_DESC_WRITE_ADDR: '{default: REG_BIT_RW}, + REG_DESC_WRITE_LEN_AND_TAG: '{default: REG_BIT_RW}, + REG_STATUS_WRITE_LEN: '{default: REG_BIT_RO}, + REG_STATUS_WRITE_CONFIG: '{default: REG_BIT_RO} +}; - // REG_WINDOW_SIZE - '{default: REG_BIT_RW}, - - // REG_ERROR - '{default: REG_BIT_RO}, - - // REG_DESC_READ_ADDR - '{default: REG_BIT_RW}, - - // REG_DESC_READ_LEN - '{default: REG_BIT_RW}, - - // REG_DESC_READ_CONFIG - '{default: REG_BIT_RW}, - - // REG_READ_STATUS - '{default: REG_BIT_RO}, - - // REG_DESC_WRITE_ADDR - '{default: REG_BIT_RW}, - - // REG_DESC_WRITE_LEN_AND_TAG - '{default: REG_BIT_RW}, - - // REG_STATUS_WRITE_LEN - '{default: REG_BIT_RO}, - - // REG_STATUS_WRITE_CONFIG - '{default: REG_BIT_RO} - }; - - localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0] AXI4L_REG_MAP_EXAMPLE_REG_RST = '{ + localparam logic [CTRL_REG_MAP_N_REGS-1:0][31:0] CTRL_REG_MAP_REG_RST = '{ 32'h0000_0000, 32'h0000_0000, 32'h0000_0000,