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add window_size register

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This commit is contained in:
otroubi
2026-07-10 14:15:17 +03:00
parent 7bd1aa68da
commit c0a2f0e403
4 changed files with 125 additions and 91 deletions
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4
rtl/controller/src/axi4l_reg_map_controller.sv
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@ -9,6 +9,7 @@ module axi4l_reg_map_controller #(
// dac adc registers // dac adc registers
output logic start_o, output logic start_o,
output logic send_o, output logic send_o,
output logic cfg_bus_valid_o,
output logic [31:0] pulse_width_o, output logic [31:0] pulse_width_o,
output logic [31:0] pulse_period_o, output logic [31:0] pulse_period_o,
output logic [31:0] pulse_num_o, output logic [31:0] pulse_num_o,
@ -60,7 +61,7 @@ module axi4l_reg_map_controller #(
always_comb begin always_comb begin
reg_i = '0; reg_i = '0;
reg_i[REG_STATUS][7:0] = busy_i; reg_i[REG_STATUS][0] = busy_i;
reg_i[REG_ERROR][7:0] = error_code_i; reg_i[REG_ERROR][7:0] = error_code_i;
reg_i[REG_READ_STATUS] = status_read_i; reg_i[REG_READ_STATUS] = status_read_i;
@ -72,6 +73,7 @@ module axi4l_reg_map_controller #(
assign start_o = reg_pulse[REG_CONTROL][0]; assign start_o = reg_pulse[REG_CONTROL][0];
assign rst_soft_o = reg_pulse[REG_CONTROL][1]; assign rst_soft_o = reg_pulse[REG_CONTROL][1];
assign send_o = reg_pulse[REG_CONTROL][2]; assign send_o = reg_pulse[REG_CONTROL][2];
assign cfg_bus_valid_o = reg_pulse[REG_CONTROL][3];
assign pulse_width_o = reg_o[REG_DAC_WIDTH]; assign pulse_width_o = reg_o[REG_DAC_WIDTH];
assign pulse_period_o = reg_o[REG_DAC_PERIOD]; assign pulse_period_o = reg_o[REG_DAC_PERIOD];
assign pulse_num_o = reg_o[REG_DAC_PULSE_NUM]; assign pulse_num_o = reg_o[REG_DAC_PULSE_NUM];

11
rtl/controller/src/controller.sv
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@ -10,7 +10,7 @@ module control #(
// adc_clk_in domain // adc_clk_in domain
input logic finish, input logic finish,
input logic [127:0] cfg_bus_input, input logic [159:0] cfg_bus_input,
input logic cfg_bus_valid, input logic cfg_bus_valid,
input logic start, input logic start,
@ -26,6 +26,7 @@ module control #(
// adc_clk_in domain outputs // adc_clk_in domain outputs
output logic [31:0] adc_pulse_period, output logic [31:0] adc_pulse_period,
output logic [15:0] adc_pulse_num, output logic [15:0] adc_pulse_num,
output logic [31:0] adc_window_size,
// pulse outputs // pulse outputs
output logic dac_start, output logic dac_start,
@ -155,7 +156,7 @@ module control #(
end end
end end
logic [127:0] cfg_bus; logic [159:0] cfg_bus;
always_ff @(posedge ctrl_clk or posedge ctrl_rst) begin always_ff @(posedge ctrl_clk or posedge ctrl_rst) begin
if (ctrl_rst) begin if (ctrl_rst) begin
@ -316,8 +317,9 @@ module control #(
cfg_req_sync_adc_d <= 1'b0; cfg_req_sync_adc_d <= 1'b0;
cfg_ack_toggle_adc <= 1'b0; cfg_ack_toggle_adc <= 1'b0;
adc_pulse_period <= '0; adc_pulse_period <= '0;
adc_pulse_num <= '0; adc_pulse_num <= '0;
adc_window_size <= '0;
end else begin end else begin
cfg_req_meta_adc <= cfg_req_toggle_adc; cfg_req_meta_adc <= cfg_req_toggle_adc;
cfg_req_sync_adc <= cfg_req_meta_adc; cfg_req_sync_adc <= cfg_req_meta_adc;
@ -326,6 +328,7 @@ module control #(
if (cfg_req_pulse_adc) begin if (cfg_req_pulse_adc) begin
adc_pulse_period <= cfg_bus[127:96]; adc_pulse_period <= cfg_bus[127:96];
adc_pulse_num <= cfg_bus[79:64]; adc_pulse_num <= cfg_bus[79:64];
adc_window_size <= cfg_bus[159:128];
cfg_ack_toggle_adc <= ~cfg_ack_toggle_adc; cfg_ack_toggle_adc <= ~cfg_ack_toggle_adc;
end end

179
rtl/controller/tests/controller_tb.sv
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@ -35,7 +35,7 @@ module tb_control;
logic finish; logic finish;
logic [127:0] cfg_bus_input; logic [159:0] cfg_bus_input;
logic cfg_bus_valid; logic cfg_bus_valid;
logic start; logic start;
@ -53,6 +53,7 @@ module tb_control;
logic [31:0] adc_pulse_period; logic [31:0] adc_pulse_period;
logic [15:0] adc_pulse_num; logic [15:0] adc_pulse_num;
logic [31:0] adc_window_size;
logic dac_start; logic dac_start;
logic adc_start; logic adc_start;
@ -89,6 +90,7 @@ module tb_control;
.adc_pulse_period (adc_pulse_period), .adc_pulse_period (adc_pulse_period),
.adc_pulse_num (adc_pulse_num), .adc_pulse_num (adc_pulse_num),
.adc_window_size (adc_window_size),
.dac_start (dac_start), .dac_start (dac_start),
.adc_start (adc_start), .adc_start (adc_start),
@ -167,34 +169,39 @@ module tb_control;
endtask endtask
task automatic send_set_data( task automatic send_set_data(
input logic [31:0] pulse_width, input logic [31:0] pulse_width,
input logic [31:0] pulse_period, input logic [31:0] pulse_period,
input logic [15:0] pulse_num, input logic [15:0] pulse_num,
input logic [15:0] pulse_height_raw, input logic [15:0] pulse_height_raw,
input logic [31:0] pulse_period_adc input logic [31:0] pulse_period_adc,
); input logic [31:0] window_size
logic [127:0] payload; );
begin
payload = { logic [159:0] payload;
pulse_period_adc,
pulse_height_raw,
pulse_num,
pulse_period,
pulse_width
};
@(negedge ctrl_clk); begin
cfg_bus_input <= payload; payload = {
cfg_bus_valid <= 1'b1; window_size,
pulse_period_adc,
pulse_height_raw,
pulse_num,
pulse_period,
pulse_width
};
@(posedge ctrl_clk); @(negedge ctrl_clk);
cfg_bus_valid <= 1'b0; cfg_bus_input <= payload;
cfg_bus_input <= '0; cfg_bus_valid <= 1'b1;
end
endtask @(posedge ctrl_clk);
cfg_bus_valid <= 1'b0;
cfg_bus_input <= '0;
end
endtask
task automatic pulse_finish; task automatic pulse_finish;
begin begin
@ -283,43 +290,48 @@ module tb_control;
endtask endtask
task automatic wait_cfg_applied( task automatic wait_cfg_applied(
input logic [31:0] exp_pulse_width,
input logic [31:0] exp_pulse_period,
input logic [15:0] exp_pulse_num,
input logic [15:0] exp_pulse_height_raw,
input logic [31:0] exp_pulse_period_adc,
input int max_cycles = 200
);
logic [DAC_DATA_WIDTH-1:0] exp_dac_height;
int i;
begin input logic [31:0] exp_pulse_width,
input logic [31:0] exp_pulse_period,
input logic [15:0] exp_pulse_num,
input logic [15:0] exp_pulse_height_raw,
input logic [31:0] exp_pulse_period_adc,
input logic [31:0] exp_window_size,
input int max_cycles = 200
);
exp_dac_height = exp_pulse_height_raw[DAC_DATA_WIDTH-1:0]; logic [DAC_DATA_WIDTH-1:0] exp_height;
for (i = 0; i < max_cycles; i++) begin int i;
@(posedge ctrl_clk);
if ((dac_pulse_width === exp_pulse_width) && begin
(dac_pulse_period === exp_pulse_period) &&
(dac_pulse_num === exp_pulse_num) &&
(dac_pulse_height === exp_dac_height) &&
(adc_pulse_period === exp_pulse_period_adc) &&
(adc_pulse_num === exp_pulse_num))
return;
end
$fatal(1, exp_height = exp_pulse_height_raw[DAC_DATA_WIDTH-1:0];
"Timeout waiting config outputs. Got: dac_width=%h dac_period=%h dac_num=%h dac_height=%h adc_period=%h adc_num=%h",
dac_pulse_width, for(i=0;i<max_cycles;i++) begin
dac_pulse_period,
dac_pulse_num, @(posedge ctrl_clk);
dac_pulse_height,
adc_pulse_period, if(
adc_pulse_num
); dac_pulse_width == exp_pulse_width &&
end dac_pulse_period == exp_pulse_period &&
endtask dac_pulse_num == exp_pulse_num &&
dac_pulse_height == exp_height &&
adc_pulse_period == exp_pulse_period_adc &&
adc_pulse_num == exp_pulse_num &&
adc_window_size == exp_window_size
)
return;
end
$fatal("Configuration timeout");
end
endtask
//------------------------------------------------------------ //------------------------------------------------------------
// Test sequence // Test sequence
@ -330,6 +342,7 @@ module tb_control;
logic [15:0] test_pulse_num; logic [15:0] test_pulse_num;
logic [15:0] test_pulse_height_raw; logic [15:0] test_pulse_height_raw;
logic [31:0] test_pulse_period_adc; logic [31:0] test_pulse_period_adc;
logic [31:0] test_window_size;
initial begin initial begin
// defaults // defaults
@ -347,6 +360,7 @@ module tb_control;
test_pulse_num = 16'hA1B2; test_pulse_num = 16'hA1B2;
test_pulse_height_raw = 16'h0CDE; // for DAC_DATA_WIDTH=12 => 12'hCDE test_pulse_height_raw = 16'h0CDE; // for DAC_DATA_WIDTH=12 => 12'hCDE
test_pulse_period_adc = 32'h50607080; test_pulse_period_adc = 32'h50607080;
test_window_size = 32'hABCDEF55;
repeat (10) @(posedge ctrl_clk); repeat (10) @(posedge ctrl_clk);
rst_n = 1'b1; rst_n = 1'b1;
@ -387,20 +401,26 @@ module tb_control;
$display("[%0t] TEST 2: set_data", $time); $display("[%0t] TEST 2: set_data", $time);
send_set_data( send_set_data(
test_pulse_width,
test_pulse_period, test_pulse_width,
test_pulse_num, test_pulse_period,
test_pulse_height_raw, test_pulse_num,
test_pulse_period_adc test_pulse_height_raw,
); test_pulse_period_adc,
test_window_size
);
wait_cfg_applied( wait_cfg_applied(
test_pulse_width,
test_pulse_period, test_pulse_width,
test_pulse_num, test_pulse_period,
test_pulse_height_raw, test_pulse_num,
test_pulse_period_adc test_pulse_height_raw,
); test_pulse_period_adc,
test_window_size
);
if (dac_pulse_width !== 32'h11223344) begin if (dac_pulse_width !== 32'h11223344) begin
$fatal(1, $fatal(1,
@ -450,6 +470,14 @@ module tb_control;
); );
end end
if(adc_window_size != test_window_size)
$fatal(
"adc_window_size mismatch. got=%h expected=%h",
adc_window_size,
test_window_size
);
$display("[%0t] TEST 2 passed", $time); $display("[%0t] TEST 2 passed", $time);
repeat (20) @(posedge ctrl_clk); repeat (20) @(posedge ctrl_clk);
@ -551,6 +579,7 @@ module tb_control;
test_pulse_num = 16'h1A2B; test_pulse_num = 16'h1A2B;
test_pulse_height_raw = 16'hC0ED; // for DAC_DATA_WIDTH=12 => 12'hCDE test_pulse_height_raw = 16'hC0ED; // for DAC_DATA_WIDTH=12 => 12'hCDE
test_pulse_period_adc = 32'h56565656; test_pulse_period_adc = 32'h56565656;
test_window_size = 32'h01020304;
$display("[%0t] TEST 2.1: set_data", $time); $display("[%0t] TEST 2.1: set_data", $time);
@ -559,7 +588,8 @@ module tb_control;
test_pulse_period, test_pulse_period,
test_pulse_num, test_pulse_num,
test_pulse_height_raw, test_pulse_height_raw,
test_pulse_period_adc test_pulse_period_adc,
test_window_size
); );
wait_cfg_applied( wait_cfg_applied(
@ -567,7 +597,8 @@ module tb_control;
test_pulse_period, test_pulse_period,
test_pulse_num, test_pulse_num,
test_pulse_height_raw, test_pulse_height_raw,
test_pulse_period_adc test_pulse_period_adc,
test_window_size
); );
if (dac_pulse_width !== 32'h12121212) begin if (dac_pulse_width !== 32'h12121212) begin
@ -622,17 +653,17 @@ module tb_control;
send_cmd(8'hF0); send_cmd(8'hF0);
wait_dac_start_count(1); wait_dac_start_count(2);
wait_adc_start_count(1); wait_adc_start_count(2);
if (dac_start_count != 1) begin if (dac_start_count != 2) begin
$fatal(1, $fatal(1,
"Expected exactly one dac_start pulse after first start, got %0d", "Expected exactly one dac_start pulse after first start, got %0d",
dac_start_count dac_start_count
); );
end end
if (adc_start_count != 1) begin if (adc_start_count != 2) begin
$fatal(1, $fatal(1,
"Expected exactly one adc_start pulse after first start, got %0d", "Expected exactly one adc_start pulse after first start, got %0d",
adc_start_count adc_start_count

22
rtl/controller/tests/tb_control_behav.wcfg
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@ -11,12 +11,12 @@
</db_ref> </db_ref>
</db_ref_list> </db_ref_list>
<zoom_setting> <zoom_setting>
<ZoomStartTime time="0.000 ns"></ZoomStartTime> <ZoomStartTime time="160.614 ns"></ZoomStartTime>
<ZoomEndTime time="1,269.181 ns"></ZoomEndTime> <ZoomEndTime time="1,564.737 ns"></ZoomEndTime>
<Cursor1Time time="580.000 ns"></Cursor1Time> <Cursor1Time time="1,330.716 ns"></Cursor1Time>
</zoom_setting> </zoom_setting>
<column_width_setting> <column_width_setting>
<NameColumnWidth column_width="487"></NameColumnWidth> <NameColumnWidth column_width="479"></NameColumnWidth>
<ValueColumnWidth column_width="116"></ValueColumnWidth> <ValueColumnWidth column_width="116"></ValueColumnWidth>
</column_width_setting> </column_width_setting>
<WVObjectSize size="34" /> <WVObjectSize size="34" />
@ -78,15 +78,9 @@
<obj_property name="CustomSignalColor">#FF0080</obj_property> <obj_property name="CustomSignalColor">#FF0080</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property> <obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/tb_control/dut/cfg_busy" type="logic">
<obj_property name="ElementShortName">cfg_busy</obj_property>
<obj_property name="ObjectShortName">cfg_busy</obj_property>
<obj_property name="CustomSignalColor">#F0E68C</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject fp_name="/tb_control/cfg_bus_input" type="array"> <wvobject fp_name="/tb_control/cfg_bus_input" type="array">
<obj_property name="ElementShortName">cfg_bus_input[127:0]</obj_property> <obj_property name="ElementShortName">cfg_bus_input[159:0]</obj_property>
<obj_property name="ObjectShortName">cfg_bus_input[127:0]</obj_property> <obj_property name="ObjectShortName">cfg_bus_input[159:0]</obj_property>
<obj_property name="CustomSignalColor">#FF0080</obj_property> <obj_property name="CustomSignalColor">#FF0080</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property> <obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject> </wvobject>
@ -127,6 +121,10 @@
<obj_property name="CustomSignalColor">#FFA500</obj_property> <obj_property name="CustomSignalColor">#FFA500</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property> <obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/tb_control/adc_window_size" type="array">
<obj_property name="ElementShortName">adc_window_size[31:0]</obj_property>
<obj_property name="ObjectShortName">adc_window_size[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/tb_control/dac_start" type="logic"> <wvobject fp_name="/tb_control/dac_start" type="logic">
<obj_property name="ElementShortName">dac_start</obj_property> <obj_property name="ElementShortName">dac_start</obj_property>
<obj_property name="ObjectShortName">dac_start</obj_property> <obj_property name="ObjectShortName">dac_start</obj_property>