diff --git a/rtl/controller/src/axi4l_reg_map_controller.sv b/rtl/controller/src/axi4l_reg_map_controller.sv index bafb007..35ab25b 100644 --- a/rtl/controller/src/axi4l_reg_map_controller.sv +++ b/rtl/controller/src/axi4l_reg_map_controller.sv @@ -9,6 +9,7 @@ module axi4l_reg_map_controller #( // dac adc registers output logic start_o, output logic send_o, + output logic cfg_bus_valid_o, output logic [31:0] pulse_width_o, output logic [31:0] pulse_period_o, output logic [31:0] pulse_num_o, @@ -60,7 +61,7 @@ module axi4l_reg_map_controller #( always_comb begin reg_i = '0; - reg_i[REG_STATUS][7:0] = busy_i; + reg_i[REG_STATUS][0] = busy_i; reg_i[REG_ERROR][7:0] = error_code_i; reg_i[REG_READ_STATUS] = status_read_i; @@ -72,6 +73,7 @@ module axi4l_reg_map_controller #( assign start_o = reg_pulse[REG_CONTROL][0]; assign rst_soft_o = reg_pulse[REG_CONTROL][1]; assign send_o = reg_pulse[REG_CONTROL][2]; + assign cfg_bus_valid_o = reg_pulse[REG_CONTROL][3]; assign pulse_width_o = reg_o[REG_DAC_WIDTH]; assign pulse_period_o = reg_o[REG_DAC_PERIOD]; assign pulse_num_o = reg_o[REG_DAC_PULSE_NUM]; diff --git a/rtl/controller/src/controller.sv b/rtl/controller/src/controller.sv index c79ffa0..f6b9275 100644 --- a/rtl/controller/src/controller.sv +++ b/rtl/controller/src/controller.sv @@ -10,7 +10,7 @@ module control #( // adc_clk_in domain input logic finish, - input logic [127:0] cfg_bus_input, + input logic [159:0] cfg_bus_input, input logic cfg_bus_valid, input logic start, @@ -26,6 +26,7 @@ module control #( // adc_clk_in domain outputs output logic [31:0] adc_pulse_period, output logic [15:0] adc_pulse_num, + output logic [31:0] adc_window_size, // pulse outputs output logic dac_start, @@ -155,7 +156,7 @@ module control #( end end - logic [127:0] cfg_bus; + logic [159:0] cfg_bus; always_ff @(posedge ctrl_clk or posedge ctrl_rst) begin if (ctrl_rst) begin @@ -316,8 +317,9 @@ module control #( cfg_req_sync_adc_d <= 1'b0; cfg_ack_toggle_adc <= 1'b0; - adc_pulse_period <= '0; - adc_pulse_num <= '0; + adc_pulse_period <= '0; + adc_pulse_num <= '0; + adc_window_size <= '0; end else begin cfg_req_meta_adc <= cfg_req_toggle_adc; cfg_req_sync_adc <= cfg_req_meta_adc; @@ -326,6 +328,7 @@ module control #( if (cfg_req_pulse_adc) begin adc_pulse_period <= cfg_bus[127:96]; adc_pulse_num <= cfg_bus[79:64]; + adc_window_size <= cfg_bus[159:128]; cfg_ack_toggle_adc <= ~cfg_ack_toggle_adc; end diff --git a/rtl/controller/tests/controller_tb.sv b/rtl/controller/tests/controller_tb.sv index 56fb55b..14119d9 100644 --- a/rtl/controller/tests/controller_tb.sv +++ b/rtl/controller/tests/controller_tb.sv @@ -35,7 +35,7 @@ module tb_control; logic finish; - logic [127:0] cfg_bus_input; + logic [159:0] cfg_bus_input; logic cfg_bus_valid; logic start; @@ -53,6 +53,7 @@ module tb_control; logic [31:0] adc_pulse_period; logic [15:0] adc_pulse_num; + logic [31:0] adc_window_size; logic dac_start; logic adc_start; @@ -89,6 +90,7 @@ module tb_control; .adc_pulse_period (adc_pulse_period), .adc_pulse_num (adc_pulse_num), + .adc_window_size (adc_window_size), .dac_start (dac_start), .adc_start (adc_start), @@ -167,34 +169,39 @@ module tb_control; endtask task automatic send_set_data( - input logic [31:0] pulse_width, - input logic [31:0] pulse_period, - input logic [15:0] pulse_num, - input logic [15:0] pulse_height_raw, - input logic [31:0] pulse_period_adc - ); - logic [127:0] payload; - begin + input logic [31:0] pulse_width, + input logic [31:0] pulse_period, + input logic [15:0] pulse_num, + input logic [15:0] pulse_height_raw, + input logic [31:0] pulse_period_adc, + input logic [31:0] window_size +); - payload = { - pulse_period_adc, - pulse_height_raw, - pulse_num, - pulse_period, - pulse_width - }; +logic [159:0] payload; - @(negedge ctrl_clk); +begin - cfg_bus_input <= payload; - cfg_bus_valid <= 1'b1; + payload = { + window_size, + pulse_period_adc, + pulse_height_raw, + pulse_num, + pulse_period, + pulse_width + }; - @(posedge ctrl_clk); + @(negedge ctrl_clk); - cfg_bus_valid <= 1'b0; - cfg_bus_input <= '0; - end - endtask + cfg_bus_input <= payload; + cfg_bus_valid <= 1'b1; + + @(posedge ctrl_clk); + + cfg_bus_valid <= 1'b0; + cfg_bus_input <= '0; + +end +endtask task automatic pulse_finish; begin @@ -283,43 +290,48 @@ module tb_control; endtask task automatic wait_cfg_applied( - input logic [31:0] exp_pulse_width, - input logic [31:0] exp_pulse_period, - input logic [15:0] exp_pulse_num, - input logic [15:0] exp_pulse_height_raw, - input logic [31:0] exp_pulse_period_adc, - input int max_cycles = 200 - ); - logic [DAC_DATA_WIDTH-1:0] exp_dac_height; - int i; - begin + input logic [31:0] exp_pulse_width, + input logic [31:0] exp_pulse_period, + input logic [15:0] exp_pulse_num, + input logic [15:0] exp_pulse_height_raw, + input logic [31:0] exp_pulse_period_adc, + input logic [31:0] exp_window_size, + input int max_cycles = 200 +); - exp_dac_height = exp_pulse_height_raw[DAC_DATA_WIDTH-1:0]; +logic [DAC_DATA_WIDTH-1:0] exp_height; - for (i = 0; i < max_cycles; i++) begin - @(posedge ctrl_clk); +int i; - if ((dac_pulse_width === exp_pulse_width) && - (dac_pulse_period === exp_pulse_period) && - (dac_pulse_num === exp_pulse_num) && - (dac_pulse_height === exp_dac_height) && - (adc_pulse_period === exp_pulse_period_adc) && - (adc_pulse_num === exp_pulse_num)) - return; - end +begin - $fatal(1, - "Timeout waiting config outputs. Got: dac_width=%h dac_period=%h dac_num=%h dac_height=%h adc_period=%h adc_num=%h", - dac_pulse_width, - dac_pulse_period, - dac_pulse_num, - dac_pulse_height, - adc_pulse_period, - adc_pulse_num - ); - end - endtask + exp_height = exp_pulse_height_raw[DAC_DATA_WIDTH-1:0]; + + for(i=0;i 12'hCDE test_pulse_period_adc = 32'h50607080; + test_window_size = 32'hABCDEF55; repeat (10) @(posedge ctrl_clk); rst_n = 1'b1; @@ -387,20 +401,26 @@ module tb_control; $display("[%0t] TEST 2: set_data", $time); send_set_data( - test_pulse_width, - test_pulse_period, - test_pulse_num, - test_pulse_height_raw, - test_pulse_period_adc - ); + + test_pulse_width, + test_pulse_period, + test_pulse_num, + test_pulse_height_raw, + test_pulse_period_adc, + test_window_size + +); wait_cfg_applied( - test_pulse_width, - test_pulse_period, - test_pulse_num, - test_pulse_height_raw, - test_pulse_period_adc - ); + + test_pulse_width, + test_pulse_period, + test_pulse_num, + test_pulse_height_raw, + test_pulse_period_adc, + test_window_size + +); if (dac_pulse_width !== 32'h11223344) begin $fatal(1, @@ -449,6 +469,14 @@ module tb_control; 16'hA1B2 ); end + + if(adc_window_size != test_window_size) + + $fatal( + "adc_window_size mismatch. got=%h expected=%h", + adc_window_size, + test_window_size + ); $display("[%0t] TEST 2 passed", $time); @@ -551,6 +579,7 @@ module tb_control; test_pulse_num = 16'h1A2B; test_pulse_height_raw = 16'hC0ED; // for DAC_DATA_WIDTH=12 => 12'hCDE test_pulse_period_adc = 32'h56565656; + test_window_size = 32'h01020304; $display("[%0t] TEST 2.1: set_data", $time); @@ -559,7 +588,8 @@ module tb_control; test_pulse_period, test_pulse_num, test_pulse_height_raw, - test_pulse_period_adc + test_pulse_period_adc, + test_window_size ); wait_cfg_applied( @@ -567,7 +597,8 @@ module tb_control; test_pulse_period, test_pulse_num, test_pulse_height_raw, - test_pulse_period_adc + test_pulse_period_adc, + test_window_size ); if (dac_pulse_width !== 32'h12121212) begin @@ -622,17 +653,17 @@ module tb_control; send_cmd(8'hF0); - wait_dac_start_count(1); - wait_adc_start_count(1); + wait_dac_start_count(2); + wait_adc_start_count(2); - if (dac_start_count != 1) begin + if (dac_start_count != 2) begin $fatal(1, "Expected exactly one dac_start pulse after first start, got %0d", dac_start_count ); end - if (adc_start_count != 1) begin + if (adc_start_count != 2) begin $fatal(1, "Expected exactly one adc_start pulse after first start, got %0d", adc_start_count diff --git a/rtl/controller/tests/tb_control_behav.wcfg b/rtl/controller/tests/tb_control_behav.wcfg index 656c219..16048c6 100644 --- a/rtl/controller/tests/tb_control_behav.wcfg +++ b/rtl/controller/tests/tb_control_behav.wcfg @@ -11,12 +11,12 @@ - - - + + + - + @@ -78,15 +78,9 @@ #FF0080 true - - cfg_busy - cfg_busy - #F0E68C - true - - cfg_bus_input[127:0] - cfg_bus_input[127:0] + cfg_bus_input[159:0] + cfg_bus_input[159:0] #FF0080 true @@ -127,6 +121,10 @@ #FFA500 true + + adc_window_size[31:0] + adc_window_size[31:0] + dac_start dac_start