add window_size register
This commit is contained in:
otroubi
@ -35,7 +35,7 @@ module tb_control;
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logic finish;
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logic [127:0] cfg_bus_input;
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logic [159:0] cfg_bus_input;
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logic cfg_bus_valid;
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logic start;
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@ -53,6 +53,7 @@ module tb_control;
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logic [31:0] adc_pulse_period;
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logic [15:0] adc_pulse_num;
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logic [31:0] adc_window_size;
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logic dac_start;
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logic adc_start;
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@ -89,6 +90,7 @@ module tb_control;
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.adc_pulse_period (adc_pulse_period),
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.adc_pulse_num (adc_pulse_num),
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.adc_window_size (adc_window_size),
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.dac_start (dac_start),
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.adc_start (adc_start),
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@ -167,34 +169,39 @@ module tb_control;
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endtask
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task automatic send_set_data(
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input logic [31:0] pulse_width,
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input logic [31:0] pulse_period,
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input logic [15:0] pulse_num,
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input logic [15:0] pulse_height_raw,
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input logic [31:0] pulse_period_adc
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);
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logic [127:0] payload;
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begin
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input logic [31:0] pulse_width,
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input logic [31:0] pulse_period,
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input logic [15:0] pulse_num,
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input logic [15:0] pulse_height_raw,
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input logic [31:0] pulse_period_adc,
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input logic [31:0] window_size
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);
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payload = {
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pulse_period_adc,
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pulse_height_raw,
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pulse_num,
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pulse_period,
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pulse_width
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};
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logic [159:0] payload;
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@(negedge ctrl_clk);
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begin
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cfg_bus_input <= payload;
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cfg_bus_valid <= 1'b1;
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payload = {
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window_size,
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pulse_period_adc,
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pulse_height_raw,
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pulse_num,
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pulse_period,
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pulse_width
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};
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@(posedge ctrl_clk);
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@(negedge ctrl_clk);
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cfg_bus_valid <= 1'b0;
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cfg_bus_input <= '0;
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end
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endtask
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cfg_bus_input <= payload;
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cfg_bus_valid <= 1'b1;
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@(posedge ctrl_clk);
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cfg_bus_valid <= 1'b0;
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cfg_bus_input <= '0;
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end
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endtask
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task automatic pulse_finish;
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begin
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@ -283,43 +290,48 @@ module tb_control;
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endtask
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task automatic wait_cfg_applied(
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input logic [31:0] exp_pulse_width,
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input logic [31:0] exp_pulse_period,
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input logic [15:0] exp_pulse_num,
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input logic [15:0] exp_pulse_height_raw,
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input logic [31:0] exp_pulse_period_adc,
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input int max_cycles = 200
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);
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logic [DAC_DATA_WIDTH-1:0] exp_dac_height;
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int i;
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begin
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input logic [31:0] exp_pulse_width,
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input logic [31:0] exp_pulse_period,
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input logic [15:0] exp_pulse_num,
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input logic [15:0] exp_pulse_height_raw,
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input logic [31:0] exp_pulse_period_adc,
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input logic [31:0] exp_window_size,
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input int max_cycles = 200
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);
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exp_dac_height = exp_pulse_height_raw[DAC_DATA_WIDTH-1:0];
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logic [DAC_DATA_WIDTH-1:0] exp_height;
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for (i = 0; i < max_cycles; i++) begin
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@(posedge ctrl_clk);
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int i;
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if ((dac_pulse_width === exp_pulse_width) &&
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(dac_pulse_period === exp_pulse_period) &&
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(dac_pulse_num === exp_pulse_num) &&
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(dac_pulse_height === exp_dac_height) &&
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(adc_pulse_period === exp_pulse_period_adc) &&
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(adc_pulse_num === exp_pulse_num))
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return;
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end
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begin
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$fatal(1,
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"Timeout waiting config outputs. Got: dac_width=%h dac_period=%h dac_num=%h dac_height=%h adc_period=%h adc_num=%h",
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dac_pulse_width,
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dac_pulse_period,
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dac_pulse_num,
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dac_pulse_height,
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adc_pulse_period,
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adc_pulse_num
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);
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end
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endtask
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exp_height = exp_pulse_height_raw[DAC_DATA_WIDTH-1:0];
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for(i=0;i<max_cycles;i++) begin
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@(posedge ctrl_clk);
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if(
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dac_pulse_width == exp_pulse_width &&
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dac_pulse_period == exp_pulse_period &&
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dac_pulse_num == exp_pulse_num &&
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dac_pulse_height == exp_height &&
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adc_pulse_period == exp_pulse_period_adc &&
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adc_pulse_num == exp_pulse_num &&
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adc_window_size == exp_window_size
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)
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return;
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end
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$fatal("Configuration timeout");
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end
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endtask
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//------------------------------------------------------------
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// Test sequence
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@ -330,6 +342,7 @@ module tb_control;
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logic [15:0] test_pulse_num;
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logic [15:0] test_pulse_height_raw;
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logic [31:0] test_pulse_period_adc;
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logic [31:0] test_window_size;
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initial begin
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// defaults
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@ -347,6 +360,7 @@ module tb_control;
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test_pulse_num = 16'hA1B2;
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test_pulse_height_raw = 16'h0CDE; // for DAC_DATA_WIDTH=12 => 12'hCDE
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test_pulse_period_adc = 32'h50607080;
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test_window_size = 32'hABCDEF55;
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repeat (10) @(posedge ctrl_clk);
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rst_n = 1'b1;
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@ -387,20 +401,26 @@ module tb_control;
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$display("[%0t] TEST 2: set_data", $time);
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send_set_data(
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test_pulse_width,
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test_pulse_period,
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test_pulse_num,
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test_pulse_height_raw,
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test_pulse_period_adc
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);
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test_pulse_width,
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test_pulse_period,
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test_pulse_num,
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test_pulse_height_raw,
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test_pulse_period_adc,
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test_window_size
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);
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wait_cfg_applied(
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test_pulse_width,
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test_pulse_period,
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test_pulse_num,
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test_pulse_height_raw,
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test_pulse_period_adc
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);
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test_pulse_width,
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test_pulse_period,
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test_pulse_num,
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test_pulse_height_raw,
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test_pulse_period_adc,
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test_window_size
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);
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if (dac_pulse_width !== 32'h11223344) begin
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$fatal(1,
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@ -449,6 +469,14 @@ module tb_control;
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16'hA1B2
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);
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end
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if(adc_window_size != test_window_size)
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$fatal(
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"adc_window_size mismatch. got=%h expected=%h",
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adc_window_size,
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test_window_size
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);
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$display("[%0t] TEST 2 passed", $time);
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@ -551,6 +579,7 @@ module tb_control;
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test_pulse_num = 16'h1A2B;
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test_pulse_height_raw = 16'hC0ED; // for DAC_DATA_WIDTH=12 => 12'hCDE
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test_pulse_period_adc = 32'h56565656;
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test_window_size = 32'h01020304;
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$display("[%0t] TEST 2.1: set_data", $time);
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@ -559,7 +588,8 @@ module tb_control;
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test_pulse_period,
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test_pulse_num,
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test_pulse_height_raw,
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test_pulse_period_adc
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test_pulse_period_adc,
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test_window_size
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);
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wait_cfg_applied(
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@ -567,7 +597,8 @@ module tb_control;
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test_pulse_period,
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test_pulse_num,
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test_pulse_height_raw,
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test_pulse_period_adc
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test_pulse_period_adc,
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test_window_size
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);
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if (dac_pulse_width !== 32'h12121212) begin
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@ -622,17 +653,17 @@ module tb_control;
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send_cmd(8'hF0);
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wait_dac_start_count(1);
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wait_adc_start_count(1);
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wait_dac_start_count(2);
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wait_adc_start_count(2);
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if (dac_start_count != 1) begin
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if (dac_start_count != 2) begin
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$fatal(1,
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"Expected exactly one dac_start pulse after first start, got %0d",
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dac_start_count
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);
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end
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if (adc_start_count != 1) begin
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if (adc_start_count != 2) begin
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$fatal(1,
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"Expected exactly one adc_start pulse after first start, got %0d",
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adc_start_count
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