add window_size register

2026-07-10 14:15:17 +03:00
parent 7bd1aa68da
commit c0a2f0e403
4 changed files with 125 additions and 91 deletions
--- a/rtl/controller/tests/controller_tb.sv
+++ b/rtl/controller/tests/controller_tb.sv
@ -35,7 +35,7 @@ module tb_control;

    logic finish;

-    logic [127:0] cfg_bus_input;
+    logic [159:0] cfg_bus_input;
    logic         cfg_bus_valid;

    logic start;
@ -53,6 +53,7 @@ module tb_control;

    logic [31:0]               adc_pulse_period;
    logic [15:0]               adc_pulse_num;
+    logic [31:0]               adc_window_size;

    logic dac_start;
    logic adc_start;
@ -89,6 +90,7 @@ module tb_control;

        .adc_pulse_period (adc_pulse_period),
        .adc_pulse_num    (adc_pulse_num),
+        .adc_window_size  (adc_window_size),

        .dac_start        (dac_start),
        .adc_start        (adc_start),
@ -167,34 +169,39 @@ module tb_control;
    endtask

    task automatic send_set_data(
-        input logic [31:0] pulse_width,
-        input logic [31:0] pulse_period,
-        input logic [15:0] pulse_num,
-        input logic [15:0] pulse_height_raw,
-        input logic [31:0] pulse_period_adc
-    );
-        logic [127:0] payload;
-        begin
+    input logic [31:0] pulse_width,
+    input logic [31:0] pulse_period,
+    input logic [15:0] pulse_num,
+    input logic [15:0] pulse_height_raw,
+    input logic [31:0] pulse_period_adc,
+    input logic [31:0] window_size
+);

-            payload = {
-                pulse_period_adc,
-                pulse_height_raw,
-                pulse_num,
-                pulse_period,
-                pulse_width
-            };
+logic [159:0] payload;

-            @(negedge ctrl_clk);
+begin

-            cfg_bus_input <= payload;
-            cfg_bus_valid <= 1'b1;
+    payload = {
+        window_size,
+        pulse_period_adc,
+        pulse_height_raw,
+        pulse_num,
+        pulse_period,
+        pulse_width
+    };

-            @(posedge ctrl_clk);
+    @(negedge ctrl_clk);

-            cfg_bus_valid <= 1'b0;
-            cfg_bus_input <= '0;
-        end
-    endtask
+    cfg_bus_input <= payload;
+    cfg_bus_valid <= 1'b1;
+
+    @(posedge ctrl_clk);
+
+    cfg_bus_valid <= 1'b0;
+    cfg_bus_input <= '0;
+
+end
+endtask

    task automatic pulse_finish;
        begin
@ -283,43 +290,48 @@ module tb_control;
    endtask

    task automatic wait_cfg_applied(
-        input logic [31:0] exp_pulse_width,
-        input logic [31:0] exp_pulse_period,
-        input logic [15:0] exp_pulse_num,
-        input logic [15:0] exp_pulse_height_raw,
-        input logic [31:0] exp_pulse_period_adc,
-        input int max_cycles = 200
-    );
-        logic [DAC_DATA_WIDTH-1:0] exp_dac_height;
-        int i;

-        begin
+    input logic [31:0] exp_pulse_width,
+    input logic [31:0] exp_pulse_period,
+    input logic [15:0] exp_pulse_num,
+    input logic [15:0] exp_pulse_height_raw,
+    input logic [31:0] exp_pulse_period_adc,
+    input logic [31:0] exp_window_size,
+    input int max_cycles = 200
+);

-            exp_dac_height = exp_pulse_height_raw[DAC_DATA_WIDTH-1:0];
+logic [DAC_DATA_WIDTH-1:0] exp_height;

-            for (i = 0; i < max_cycles; i++) begin
-                @(posedge ctrl_clk);
+int i;

-                if ((dac_pulse_width  === exp_pulse_width) &&
-                    (dac_pulse_period === exp_pulse_period) &&
-                    (dac_pulse_num    === exp_pulse_num) &&
-                    (dac_pulse_height === exp_dac_height) &&
-                    (adc_pulse_period === exp_pulse_period_adc) &&
-                    (adc_pulse_num    === exp_pulse_num))
-                    return;
-            end
+begin

-            $fatal(1,
-                "Timeout waiting config outputs. Got: dac_width=%h dac_period=%h dac_num=%h dac_height=%h adc_period=%h adc_num=%h",
-                dac_pulse_width,
-                dac_pulse_period,
-                dac_pulse_num,
-                dac_pulse_height,
-                adc_pulse_period,
-                adc_pulse_num
-            );
-        end
-    endtask
+    exp_height = exp_pulse_height_raw[DAC_DATA_WIDTH-1:0];
+
+    for(i=0;i<max_cycles;i++) begin
+
+        @(posedge ctrl_clk);
+
+        if(
+
+            dac_pulse_width  == exp_pulse_width &&
+            dac_pulse_period == exp_pulse_period &&
+            dac_pulse_num    == exp_pulse_num &&
+            dac_pulse_height == exp_height &&
+
+            adc_pulse_period == exp_pulse_period_adc &&
+            adc_pulse_num    == exp_pulse_num &&
+            adc_window_size  == exp_window_size
+
+        )
+            return;
+
+    end
+
+    $fatal("Configuration timeout");
+
+end
+endtask
    
        //------------------------------------------------------------
    // Test sequence
@ -330,6 +342,7 @@ module tb_control;
    logic [15:0] test_pulse_num;
    logic [15:0] test_pulse_height_raw;
    logic [31:0] test_pulse_period_adc;
+    logic [31:0] test_window_size;

    initial begin
        // defaults
@ -347,6 +360,7 @@ module tb_control;
        test_pulse_num        = 16'hA1B2;
        test_pulse_height_raw = 16'h0CDE; // for DAC_DATA_WIDTH=12 => 12'hCDE
        test_pulse_period_adc = 32'h50607080;
+        test_window_size      = 32'hABCDEF55;

        repeat (10) @(posedge ctrl_clk);
        rst_n = 1'b1;
@ -387,20 +401,26 @@ module tb_control;
        $display("[%0t] TEST 2: set_data", $time);

        send_set_data(
-            test_pulse_width,
-            test_pulse_period,
-            test_pulse_num,
-            test_pulse_height_raw,
-            test_pulse_period_adc
-        );
+
+    test_pulse_width,
+    test_pulse_period,
+    test_pulse_num,
+    test_pulse_height_raw,
+    test_pulse_period_adc,
+    test_window_size
+
+);

        wait_cfg_applied(
-            test_pulse_width,
-            test_pulse_period,
-            test_pulse_num,
-            test_pulse_height_raw,
-            test_pulse_period_adc
-        );
+
+    test_pulse_width,
+    test_pulse_period,
+    test_pulse_num,
+    test_pulse_height_raw,
+    test_pulse_period_adc,
+    test_window_size
+
+);

        if (dac_pulse_width !== 32'h11223344) begin
            $fatal(1,
@ -449,6 +469,14 @@ module tb_control;
                16'hA1B2
            );
        end
+        
+        if(adc_window_size != test_window_size)
+
+    $fatal(
+        "adc_window_size mismatch. got=%h expected=%h",
+        adc_window_size,
+        test_window_size
+    );

        $display("[%0t] TEST 2 passed", $time);

@ -551,6 +579,7 @@ module tb_control;
        test_pulse_num        = 16'h1A2B;
        test_pulse_height_raw = 16'hC0ED; // for DAC_DATA_WIDTH=12 => 12'hCDE
        test_pulse_period_adc = 32'h56565656;
+        test_window_size      = 32'h01020304;
        
        $display("[%0t] TEST 2.1: set_data", $time);

@ -559,7 +588,8 @@ module tb_control;
            test_pulse_period,
            test_pulse_num,
            test_pulse_height_raw,
-            test_pulse_period_adc
+            test_pulse_period_adc,
+            test_window_size
        );

        wait_cfg_applied(
@ -567,7 +597,8 @@ module tb_control;
            test_pulse_period,
            test_pulse_num,
            test_pulse_height_raw,
-            test_pulse_period_adc
+            test_pulse_period_adc,
+            test_window_size
        );

        if (dac_pulse_width !== 32'h12121212) begin
@ -622,17 +653,17 @@ module tb_control;

        send_cmd(8'hF0);

-        wait_dac_start_count(1);
-        wait_adc_start_count(1);
+        wait_dac_start_count(2);
+        wait_adc_start_count(2);

-        if (dac_start_count != 1) begin
+        if (dac_start_count != 2) begin
            $fatal(1,
                "Expected exactly one dac_start pulse after first start, got %0d",
                dac_start_count
            );
        end

-        if (adc_start_count != 1) begin
+        if (adc_start_count != 2) begin
            $fatal(1,
                "Expected exactly one adc_start pulse after first start, got %0d",
                adc_start_count
--- a/rtl/controller/tests/tb_control_behav.wcfg
+++ b/rtl/controller/tests/tb_control_behav.wcfg
@ -11,12 +11,12 @@
      </db_ref>
   </db_ref_list>
   <zoom_setting>
-      <ZoomStartTime time="0.000 ns"></ZoomStartTime>
-      <ZoomEndTime time="1,269.181 ns"></ZoomEndTime>
-      <Cursor1Time time="580.000 ns"></Cursor1Time>
+      <ZoomStartTime time="160.614 ns"></ZoomStartTime>
+      <ZoomEndTime time="1,564.737 ns"></ZoomEndTime>
+      <Cursor1Time time="1,330.716 ns"></Cursor1Time>
   </zoom_setting>
   <column_width_setting>
-      <NameColumnWidth column_width="487"></NameColumnWidth>
+      <NameColumnWidth column_width="479"></NameColumnWidth>
      <ValueColumnWidth column_width="116"></ValueColumnWidth>
   </column_width_setting>
   <WVObjectSize size="34" />
@ -78,15 +78,9 @@
      <obj_property name="CustomSignalColor">#FF0080</obj_property>
      <obj_property name="UseCustomSignalColor">true</obj_property>
   </wvobject>
-   <wvobject fp_name="/tb_control/dut/cfg_busy" type="logic">
-      <obj_property name="ElementShortName">cfg_busy</obj_property>
-      <obj_property name="ObjectShortName">cfg_busy</obj_property>
-      <obj_property name="CustomSignalColor">#F0E68C</obj_property>
-      <obj_property name="UseCustomSignalColor">true</obj_property>
-   </wvobject>
   <wvobject fp_name="/tb_control/cfg_bus_input" type="array">
-      <obj_property name="ElementShortName">cfg_bus_input[127:0]</obj_property>
-      <obj_property name="ObjectShortName">cfg_bus_input[127:0]</obj_property>
+      <obj_property name="ElementShortName">cfg_bus_input[159:0]</obj_property>
+      <obj_property name="ObjectShortName">cfg_bus_input[159:0]</obj_property>
      <obj_property name="CustomSignalColor">#FF0080</obj_property>
      <obj_property name="UseCustomSignalColor">true</obj_property>
   </wvobject>
@ -127,6 +121,10 @@
      <obj_property name="CustomSignalColor">#FFA500</obj_property>
      <obj_property name="UseCustomSignalColor">true</obj_property>
   </wvobject>
+   <wvobject fp_name="/tb_control/adc_window_size" type="array">
+      <obj_property name="ElementShortName">adc_window_size[31:0]</obj_property>
+      <obj_property name="ObjectShortName">adc_window_size[31:0]</obj_property>
+   </wvobject>
   <wvobject fp_name="/tb_control/dac_start" type="logic">
      <obj_property name="ElementShortName">dac_start</obj_property>
      <obj_property name="ObjectShortName">dac_start</obj_property>