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add window_size register

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otroubi
2026-07-10 14:15:17 +03:00
parent 7bd1aa68da
commit c0a2f0e403
4 changed files with 125 additions and 91 deletions
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4
rtl/controller/src/axi4l_reg_map_controller.sv
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@ -9,6 +9,7 @@ module axi4l_reg_map_controller #(
// dac adc registers
output logic start_o,
output logic send_o,
output logic cfg_bus_valid_o,
output logic [31:0] pulse_width_o,
output logic [31:0] pulse_period_o,
output logic [31:0] pulse_num_o,
@ -60,7 +61,7 @@ module axi4l_reg_map_controller #(
always_comb begin
reg_i = '0;
reg_i[REG_STATUS][7:0] = busy_i;
reg_i[REG_STATUS][0] = busy_i;
reg_i[REG_ERROR][7:0] = error_code_i;
reg_i[REG_READ_STATUS] = status_read_i;
@ -72,6 +73,7 @@ module axi4l_reg_map_controller #(
assign start_o = reg_pulse[REG_CONTROL][0];
assign rst_soft_o = reg_pulse[REG_CONTROL][1];
assign send_o = reg_pulse[REG_CONTROL][2];
assign cfg_bus_valid_o = reg_pulse[REG_CONTROL][3];
assign pulse_width_o = reg_o[REG_DAC_WIDTH];
assign pulse_period_o = reg_o[REG_DAC_PERIOD];
assign pulse_num_o = reg_o[REG_DAC_PULSE_NUM];