add window_size register

rtl/controller/src/axi4l_reg_map_controller.sv

@@ -9,6 +9,7 @@ module axi4l_reg_map_controller #(
 // dac adc registers
   output logic        start_o,
   output logic        send_o,
+  output logic        cfg_bus_valid_o,
   output logic [31:0] pulse_width_o,
   output logic [31:0] pulse_period_o,
   output logic [31:0] pulse_num_o,
@@ -60,7 +61,7 @@ module axi4l_reg_map_controller #(
   always_comb begin
     reg_i = '0;
 
-    reg_i[REG_STATUS][7:0] = busy_i;
+    reg_i[REG_STATUS][0] = busy_i;
     reg_i[REG_ERROR][7:0] = error_code_i;
 
     reg_i[REG_READ_STATUS] = status_read_i;
@@ -72,6 +73,7 @@ module axi4l_reg_map_controller #(
   assign start_o                  = reg_pulse[REG_CONTROL][0];
   assign rst_soft_o               = reg_pulse[REG_CONTROL][1];
   assign send_o                   = reg_pulse[REG_CONTROL][2];
+  assign cfg_bus_valid_o          = reg_pulse[REG_CONTROL][3];
   assign pulse_width_o            = reg_o[REG_DAC_WIDTH];
   assign pulse_period_o           = reg_o[REG_DAC_PERIOD];
   assign pulse_num_o              = reg_o[REG_DAC_PULSE_NUM];

rtl/controller/src/controller.sv

@@ -10,7 +10,7 @@ module control #(
 
     // adc_clk_in domain
     input  logic                       finish,
-    input  logic [127:0]               cfg_bus_input,
+    input  logic [159:0]               cfg_bus_input,
     input  logic                       cfg_bus_valid,
     input  logic                       start,
 
@@ -26,6 +26,7 @@ module control #(
     // adc_clk_in domain outputs
     output logic [31:0]                adc_pulse_period,
     output logic [15:0]                adc_pulse_num,
+    output logic [31:0]                adc_window_size,
 
     // pulse outputs
     output logic                       dac_start,
@@ -155,7 +156,7 @@ module control #(
         end
     end
 
-    logic [127:0] cfg_bus;
+    logic [159:0] cfg_bus;
 
     always_ff @(posedge ctrl_clk or posedge ctrl_rst) begin
         if (ctrl_rst) begin
@@ -316,8 +317,9 @@ module control #(
             cfg_req_sync_adc_d <= 1'b0;
             cfg_ack_toggle_adc <= 1'b0;
 
-            adc_pulse_period   <= '0;
-            adc_pulse_num      <= '0;
+            adc_pulse_period       <= '0;
+            adc_pulse_num          <= '0;
+            adc_window_size        <= '0;
         end else begin
             cfg_req_meta_adc   <= cfg_req_toggle_adc;
             cfg_req_sync_adc   <= cfg_req_meta_adc;
@@ -326,6 +328,7 @@ module control #(
             if (cfg_req_pulse_adc) begin
                 adc_pulse_period <= cfg_bus[127:96];
                 adc_pulse_num    <= cfg_bus[79:64];
+                adc_window_size  <= cfg_bus[159:128];
 
                 cfg_ack_toggle_adc <= ~cfg_ack_toggle_adc;
             end