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change: sampler remarks

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otroubi
2026-06-10 16:22:05 +03:00
parent 5d3b761b07
commit bb65aea4f1
1 changed files with 8 additions and 8 deletions
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16
rtl/sampler/src/sampler.sv
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@ -18,10 +18,10 @@ module sampler
output logic m_axis_tvalid, output logic m_axis_tvalid,
output logic done output logic done
); );
(* MARK_DEBUG="true" *) logic [DATA_WIDTH-1:0] data_converted; logic [DATA_WIDTH-1:0] data_converted;
(* MARK_DEBUG="true" *) logic out_of_range_reg; logic out_of_range_reg;
(* MARK_DEBUG="true" *) logic [31:0] smp_num_reg, cnt_smp_num; logic [31:0] smp_num_reg, cnt_smp_num;
(* MARK_DEBUG="true" *) logic enable, enable_d; logic enable, enable_d;
generate generate
if (PROCESS_MODE) begin if (PROCESS_MODE) begin
@ -53,8 +53,8 @@ module sampler
end end
endgenerate endgenerate
(* MARK_DEBUG="true" *) logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer; logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
(* MARK_DEBUG="true" *) logic buffer_ready; logic buffer_ready;
logic [$clog2(PACK_FACTOR):0] cnt; logic [$clog2(PACK_FACTOR):0] cnt;
@ -67,7 +67,7 @@ module sampler
cnt_smp_num <= '0; cnt_smp_num <= '0;
smp_num_reg <= '0; smp_num_reg <= '0;
enable <= 0; enable <= 0;
request <= 0; done <= 0;
end end
else begin else begin
buffer_ready <= 0; buffer_ready <= 0;
@ -105,7 +105,7 @@ module sampler
cnt_smp_num <= '0; cnt_smp_num <= '0;
smp_num_reg <= '0; smp_num_reg <= '0;
enable <= 0; enable <= 0;
request <= 0; done <= 0;
end end
else begin else begin
buffer_ready <= 0; buffer_ready <= 0;