diff --git a/rtl/sampler/src/sampler.sv b/rtl/sampler/src/sampler.sv
index 2c1672c..fcdb9d8 100644
--- a/rtl/sampler/src/sampler.sv
+++ b/rtl/sampler/src/sampler.sv
@@ -18,10 +18,10 @@ module sampler
     output logic                              m_axis_tvalid,
     output logic done
     );
-   (* MARK_DEBUG="true" *) logic [DATA_WIDTH-1:0] data_converted;
-   (* MARK_DEBUG="true" *) logic out_of_range_reg;
-    (* MARK_DEBUG="true" *) logic [31:0] smp_num_reg, cnt_smp_num;
-   (* MARK_DEBUG="true" *) logic enable, enable_d;
+  logic [DATA_WIDTH-1:0] data_converted;
+  logic out_of_range_reg;
+  logic [31:0] smp_num_reg, cnt_smp_num;
+  logic enable, enable_d;
     
     generate
        if (PROCESS_MODE) begin 
@@ -53,8 +53,8 @@ module sampler
      end
     endgenerate
          
-  (* MARK_DEBUG="true" *)  logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
-  (* MARK_DEBUG="true" *)  logic buffer_ready;
+  logic [DATA_WIDTH*PACK_FACTOR-1:0] buffer;
+  logic buffer_ready;
 
     logic [$clog2(PACK_FACTOR):0] cnt;
     
@@ -67,7 +67,7 @@ module sampler
                 cnt_smp_num <= '0;
                 smp_num_reg <= '0;
                 enable <= 0;
-                request <= 0;
+                done <= 0;
             end
             else begin
                 buffer_ready <= 0;
@@ -105,7 +105,7 @@ module sampler
                 cnt_smp_num <= '0;
                 smp_num_reg <= '0;
                 enable <= 0;
-                request <= 0;
+                done <= 0;
             end
             else begin
                 buffer_ready <= 0;