add send signal to start a dma transaction

rtl/controller/src/axi4l_reg_map_controller.sv

@@ -8,6 +8,7 @@ module axi4l_reg_map_controller #(
   axi4l_if.slave s_axil,
 // dac adc registers
   output logic        start_o,
+  output logic        send_o,
   output logic [31:0] pulse_width_o,
   output logic [31:0] pulse_period_o,
   output logic [31:0] pulse_num_o,
@@ -70,6 +71,7 @@ module axi4l_reg_map_controller #(
 
   assign start_o                  = reg_pulse[REG_CONTROL][0];
   assign rst_soft_o               = reg_pulse[REG_CONTROL][1];
+  assign send_o                   = reg_pulse[REG_CONTROL][2];
   assign pulse_width_o            = reg_o[REG_DAC_WIDTH];
   assign pulse_period_o           = reg_o[REG_DAC_PERIOD];
   assign pulse_num_o              = reg_o[REG_DAC_PULSE_NUM];

rtl/controller/src/axi4l_reg_map_controller_pkg.sv

@@ -42,6 +42,7 @@ AXI write descriptor input and AXI write descriptor status output configuration
   localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0][2:0] AXI4L_REG_MAP_EXAMPLE_REG_MODE = '{
     // REG_CONTROL
     '{
+      REG_BIT_W1S,
       REG_BIT_W1S,
       REG_BIT_W1S,
       default: REG_BIT_RSVD