From a82140feda8d91d6bc32c0aebf6f678183f9cbb6 Mon Sep 17 00:00:00 2001 From: otroubi Date: Wed, 8 Jul 2026 12:49:51 +0300 Subject: [PATCH] add send signal to start a dma transaction --- rtl/controller/src/axi4l_reg_map_controller.sv | 2 ++ rtl/controller/src/axi4l_reg_map_controller_pkg.sv | 1 + 2 files changed, 3 insertions(+) diff --git a/rtl/controller/src/axi4l_reg_map_controller.sv b/rtl/controller/src/axi4l_reg_map_controller.sv index ea7d033..bafb007 100644 --- a/rtl/controller/src/axi4l_reg_map_controller.sv +++ b/rtl/controller/src/axi4l_reg_map_controller.sv @@ -8,6 +8,7 @@ module axi4l_reg_map_controller #( axi4l_if.slave s_axil, // dac adc registers output logic start_o, + output logic send_o, output logic [31:0] pulse_width_o, output logic [31:0] pulse_period_o, output logic [31:0] pulse_num_o, @@ -70,6 +71,7 @@ module axi4l_reg_map_controller #( assign start_o = reg_pulse[REG_CONTROL][0]; assign rst_soft_o = reg_pulse[REG_CONTROL][1]; + assign send_o = reg_pulse[REG_CONTROL][2]; assign pulse_width_o = reg_o[REG_DAC_WIDTH]; assign pulse_period_o = reg_o[REG_DAC_PERIOD]; assign pulse_num_o = reg_o[REG_DAC_PULSE_NUM]; diff --git a/rtl/controller/src/axi4l_reg_map_controller_pkg.sv b/rtl/controller/src/axi4l_reg_map_controller_pkg.sv index 2410842..9d30937 100644 --- a/rtl/controller/src/axi4l_reg_map_controller_pkg.sv +++ b/rtl/controller/src/axi4l_reg_map_controller_pkg.sv @@ -42,6 +42,7 @@ AXI write descriptor input and AXI write descriptor status output configuration localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0][2:0] AXI4L_REG_MAP_EXAMPLE_REG_MODE = '{ // REG_CONTROL '{ + REG_BIT_W1S, REG_BIT_W1S, REG_BIT_W1S, default: REG_BIT_RSVD