rtl: eth remove

rtl/controller/src/axi4l_reg_map_controller.sv

@@ -12,7 +12,6 @@ module axi4l_reg_map_controller #(
   output logic [31:0] pulse_period_o,
   output logic [31:0] pulse_num_o,
   output logic [31:0] pulse_height_raw_o,
-  output logic [31:0] pulse_num_ADC_o,
   output logic [31:0] pulse_period_ADC_o,
 
   // DMA read descriptors and status register
@@ -74,7 +73,6 @@ module axi4l_reg_map_controller #(
   assign pulse_period_o           = reg_o[REG_DAC_PERIOD];
   assign pulse_num_o              = reg_o[REG_DAC_PULSE_NUM];
   assign pulse_height_raw_o       = reg_o[REG_DAC_PULSE_HEIGHT]; 
-  assign pulse_num_ADC_o          = reg_o[REG_ADC_NUM];
   assign pulse_period_ADC_o       = reg_o[REG_ADC_PERIOD]; 
 
   assign desc_read_addr_o         = reg_o[REG_DESC_READ_ADDR];