From a6ade44b4d88688301276d232a1866de67641779 Mon Sep 17 00:00:00 2001 From: otroubi Date: Fri, 3 Jul 2026 16:28:08 +0300 Subject: [PATCH] rtl: eth remove --- .../src/axi4l_reg_map_controller.sv | 2 - .../src/axi4l_reg_map_controller_pkg.sv | 26 +- rtl/controller/src/controller.sv | 238 ++++-------------- 3 files changed, 65 insertions(+), 201 deletions(-) diff --git a/rtl/controller/src/axi4l_reg_map_controller.sv b/rtl/controller/src/axi4l_reg_map_controller.sv index 5bae2df..a8eec8c 100644 --- a/rtl/controller/src/axi4l_reg_map_controller.sv +++ b/rtl/controller/src/axi4l_reg_map_controller.sv @@ -12,7 +12,6 @@ module axi4l_reg_map_controller #( output logic [31:0] pulse_period_o, output logic [31:0] pulse_num_o, output logic [31:0] pulse_height_raw_o, - output logic [31:0] pulse_num_ADC_o, output logic [31:0] pulse_period_ADC_o, // DMA read descriptors and status register @@ -74,7 +73,6 @@ module axi4l_reg_map_controller #( assign pulse_period_o = reg_o[REG_DAC_PERIOD]; assign pulse_num_o = reg_o[REG_DAC_PULSE_NUM]; assign pulse_height_raw_o = reg_o[REG_DAC_PULSE_HEIGHT]; - assign pulse_num_ADC_o = reg_o[REG_ADC_NUM]; assign pulse_period_ADC_o = reg_o[REG_ADC_PERIOD]; assign desc_read_addr_o = reg_o[REG_DESC_READ_ADDR]; diff --git a/rtl/controller/src/axi4l_reg_map_controller_pkg.sv b/rtl/controller/src/axi4l_reg_map_controller_pkg.sv index 83d6950..8a4b3c6 100644 --- a/rtl/controller/src/axi4l_reg_map_controller_pkg.sv +++ b/rtl/controller/src/axi4l_reg_map_controller_pkg.sv @@ -1,6 +1,6 @@ package axi4l_reg_map_controller_pkg; - localparam int unsigned AXI4L_REG_MAP_EXAMPLE_N_REGS = 17; + localparam int unsigned AXI4L_REG_MAP_EXAMPLE_N_REGS = 16; /* dac adc configuration registers @@ -11,27 +11,26 @@ dac adc configuration registers localparam logic [31:0] REG_DAC_PERIOD = 32'd3; localparam logic [31:0] REG_DAC_PULSE_NUM = 32'd4; localparam logic [31:0] REG_DAC_PULSE_HEIGHT = 32'd5; - localparam logic [31:0] REG_ADC_NUM = 32'd6; - localparam logic [31:0] REG_ADC_PERIOD = 32'd7; - localparam logic [31:0] REG_ERROR = 32'd8; + localparam logic [31:0] REG_ADC_PERIOD = 32'd6; + localparam logic [31:0] REG_ERROR = 32'd7; /* AXI read descriptor input and AXI read descriptor status output configuration registers */ - localparam logic [31:0] REG_DESC_READ_ADDR = 32'd9; - localparam logic [31:0] REG_DESC_READ_LEN = 32'd10; - localparam logic [31:0] REG_DESC_READ_CONFIG = 32'd11; + localparam logic [31:0] REG_DESC_READ_ADDR = 32'd8; + localparam logic [31:0] REG_DESC_READ_LEN = 32'd9; + localparam logic [31:0] REG_DESC_READ_CONFIG = 32'd10; - localparam logic [31:0] REG_READ_STATUS = 32'd12; + localparam logic [31:0] REG_READ_STATUS = 32'd11; /* AXI write descriptor input and AXI write descriptor status output configuration registers */ - localparam logic [31:0] REG_DESC_WRITE_ADDR = 32'd13; - localparam logic [31:0] REG_DESC_WRITE_LEN_AND_TAG = 32'd14; + localparam logic [31:0] REG_DESC_WRITE_ADDR = 32'd12; + localparam logic [31:0] REG_DESC_WRITE_LEN_AND_TAG = 32'd13; - localparam logic [31:0] REG_STATUS_WRITE_LEN = 32'd15; - localparam logic [31:0] REG_STATUS_WRITE_CONFIG = 32'd16; + localparam logic [31:0] REG_STATUS_WRITE_LEN = 32'd14; + localparam logic [31:0] REG_STATUS_WRITE_CONFIG = 32'd15; localparam logic [2:0] REG_BIT_RSVD = 3'd0; @@ -66,9 +65,6 @@ AXI write descriptor input and AXI write descriptor status output configuration // REG_DAC_PULSE_HEIGHT '{default: REG_BIT_RW}, - // REG_ADC_NUM - '{default: REG_BIT_RW}, - // REG_ADC_PERIOD '{default: REG_BIT_RW}, diff --git a/rtl/controller/src/controller.sv b/rtl/controller/src/controller.sv index b376b81..569aa9e 100644 --- a/rtl/controller/src/controller.sv +++ b/rtl/controller/src/controller.sv @@ -1,16 +1,14 @@ module control #( - parameter int unsigned DAC_DATA_WIDTH = 12 + parameter int unsigned DAC_DATA_WIDTH = 12, + parameter int unsigned ADDR_W = 16 + parameter int unsigned DATA_W = 32 + parameter int unsigned USER_W = 1 ) ( - input logic eth_clk_in, + input logic ctrl_clk, input logic dac_clk_in, input logic adc_clk_in, input logic rst_n, - - // AXI stream slave, eth_clk_in domain - input logic [7:0] s_axis_tdata, - input logic s_axis_tvalid, - output logic s_axis_tready, - input logic s_axis_tlast, + axi4l_if.slave s_axil, // adc_clk_in domain input logic finish, @@ -32,6 +30,46 @@ module control #( output logic adc_rst ); + logic start, rst_soft; + logic [31:0] pulse_width, pulse_period, pulse_num, pulse_height_raw, pulse_period_ADC; + logic [7:0] busy, error_code; + logic [31:0] desc_read_addr, desc_read_len, desc_read_config, status_read; + logic [31:0] desc_write_addr, desc_write_len_and_tag, status_write_len, status_write_config; + + axi4l_reg_map_controller #( + .ADDR_W(ADDR_W), + .DATA_W(DATA_W), + .USER_W(USER_W) + ) axi4l_reg_map_controller_inst ( + .clk(ctrl_clk), + .rst_n(rst_n), + .s_axil(s_axil), + + .start_o(start), + .pulse_width_o(pulse_width), + .pulse_period_o(pulse_period), + .pulse_num_o(pulse_num), + .pulse_height_raw_o(pulse_height_raw), + .pulse_period_ADC_o(pulse_period_ADC), + + .desc_read_addr_o(desc_read_addr), + .desc_read_len_o(desc_read_len), + .desc_read_config_o(desc_read_config), + + .status_read_i(status_read), + + .desc_write_addr_o(desc_write_addr), + .desc_write_len_and_tag_o(desc_write_len_and_tag), + + .status_write_len_i(status_write_len), + .status_write_config_i(status_write_config), + + .rst_soft_o(rst_soft), + .busy_i(busy), + .error_code_i(error_code) + ); + + // static checks initial begin if (DAC_DATA_WIDTH > 16) begin @@ -42,21 +80,16 @@ module control #( end end - // command constants - localparam logic [7:0] CMD_SOFT_RESET = 8'h0F; - localparam logic [7:0] CMD_START = 8'hF0; - localparam logic [7:0] CMD_SET_DATA = 8'h88; - // reset synchronizers: async assert, sync deassert in each domain logic eth_rst_ff1, eth_rst_ff2; logic dac_rst_ff1, dac_rst_ff2; logic adc_rst_ff1, adc_rst_ff2; - logic eth_rst; + logic ctrl_rst; logic dac_rst_int; logic adc_rst_int; - always_ff @(posedge eth_clk_in or negedge rst_n) begin + always_ff @(posedge ctrl_clk or negedge rst_n) begin if (!rst_n) begin eth_rst_ff1 <= 1'b1; eth_rst_ff2 <= 1'b1; @@ -86,24 +119,12 @@ module control #( end end - assign eth_rst = eth_rst_ff2; + assign ctrl_rst = eth_rst_ff2; assign dac_rst_int = dac_rst_ff2; assign adc_rst_int = adc_rst_ff2; - // axi stream is always accepted. If packet is not needed, it is discarded. - assign s_axis_tready = 1'b1; - - (* MARK_DEBUG="true" *) wire axis_hs = s_axis_tvalid & s_axis_tready; // ------------------------------------------------------------------------- - // Shared 96-bit config bus in ETH domain - // - // Byte order for SET_DATA payload, little-endian: - // payload byte 0 -> cfg_bus_eth[7:0] - // payload byte 1 -> cfg_bus_eth[15:8] - // ...etc... - // payload byte 11 -> cfg_bus_eth[95:88] - // // Field layout inside cfg_bus_eth: // [31:0] pulse_width // [63:32] pulse_period @@ -113,26 +134,8 @@ module control #( // // ------------------------------------------------------------------------- (* MARK_DEBUG="true" *) logic [127:0] cfg_bus_eth; - logic [127:0] cfg_shift_eth; + assign cfg_bus_eth = {pulse_period_ADC, pulse_height_raw[15:0], pulse_num[15:0], pulse_period, pulse_width}; - // ETH-domain parser and control - typedef enum logic [2:0] { - ST_IDLE = 3'd0, - ST_RECV_CFG = 3'd1, - ST_WAIT_CFG_ACK = 3'd2, - ST_DISCARD = 3'd3 - } eth_state_t; - - (* MARK_DEBUG="true" *) eth_state_t eth_state; - - logic [3:0] cfg_byte_cnt; - - // Busy flag: set by START command, cleared by finish event from ADC domain - (* MARK_DEBUG="true" *) logic busy_flag_eth; - - // Pending ACKs for config delivery - logic cfg_wait_dac_ack; - logic cfg_wait_adc_ack; // Event toggles ETH -> DAC/ADC logic start_toggle_eth; @@ -152,8 +155,8 @@ module control #( wire cfg_ack_pulse_dac_eth = cfg_ack_toggle_dac_sync ^ cfg_ack_toggle_dac_sync_d; wire cfg_ack_pulse_adc_eth = cfg_ack_toggle_adc_sync ^ cfg_ack_toggle_adc_sync_d; - always_ff @(posedge eth_clk_in or posedge eth_rst) begin - if (eth_rst) begin + always_ff @(posedge ctrl_clk or posedge ctrl_rst) begin + if (ctrl_rst) begin cfg_ack_toggle_dac_meta <= 1'b0; cfg_ack_toggle_dac_sync <= 1'b0; cfg_ack_toggle_dac_sync_d <= 1'b0; @@ -186,8 +189,8 @@ module control #( end end - always_ff @(posedge eth_clk_in or posedge eth_rst) begin - if (eth_rst) begin + always_ff @(posedge ctrl_clk or posedge ctrl_rst) begin + if (ctrl_rst) begin finish_meta_eth <= 1'b0; finish_sync_eth <= 1'b0; finish_sync_eth_d <= 1'b0; @@ -198,139 +201,6 @@ module control #( end end - // ETH FSM - always_ff @(posedge eth_clk_in or posedge eth_rst) begin - if (eth_rst) begin - eth_state <= ST_IDLE; - cfg_byte_cnt <= '0; - cfg_shift_eth <= '0; - cfg_bus_eth <= '0; - - busy_flag_eth <= 1'b0; - - start_toggle_eth <= 1'b0; - rst_toggle_eth <= 1'b0; - - cfg_req_toggle_dac_eth <= 1'b0; - cfg_req_toggle_adc_eth <= 1'b0; - - cfg_wait_dac_ack <= 1'b0; - cfg_wait_adc_ack <= 1'b0; - end else begin - // finish always clears busy - if (finish_pulse_eth) begin - busy_flag_eth <= 1'b0; - end - - // config acks - if (cfg_ack_pulse_dac_eth) begin - cfg_wait_dac_ack <= 1'b0; - end - if (cfg_ack_pulse_adc_eth) begin - cfg_wait_adc_ack <= 1'b0; - end - - case (eth_state) - ST_IDLE: begin - cfg_byte_cnt <= '0; - cfg_shift_eth <= cfg_shift_eth; - - if (axis_hs) begin - // if busy, drop the whole packet - if (busy_flag_eth) begin - if (!s_axis_tlast) begin - eth_state <= ST_DISCARD; - end - end else begin - unique case (s_axis_tdata) - CMD_SOFT_RESET: begin - rst_toggle_eth <= ~rst_toggle_eth; - end - - CMD_START: begin - start_toggle_eth <= ~start_toggle_eth; - busy_flag_eth <= 1'b1; - end - - CMD_SET_DATA: begin - // expect exactly 12 bytes after command - if (s_axis_tlast) begin - // no payload, invalid packet - eth_state <= ST_IDLE; - end else begin - cfg_byte_cnt <= 4'd0; - cfg_shift_eth <= '0; - eth_state <= ST_RECV_CFG; - end - end - - default: begin - // unknown command: discard packet remainder if any - if (!s_axis_tlast) begin - eth_state <= ST_DISCARD; - end - end - endcase - end - end - end - - ST_RECV_CFG: begin - if (axis_hs) begin - // little endian packing - cfg_shift_eth[cfg_byte_cnt*8 +: 8] <= s_axis_tdata; - - if (cfg_byte_cnt == 4'd15) begin - // this must be the final payload byte - if (s_axis_tlast) begin - cfg_bus_eth <= {s_axis_tdata, cfg_shift_eth[119:0]}; - cfg_req_toggle_dac_eth <= ~cfg_req_toggle_dac_eth; - cfg_req_toggle_adc_eth <= ~cfg_req_toggle_adc_eth; - cfg_wait_dac_ack <= 1'b1; - cfg_wait_adc_ack <= 1'b1; - eth_state <= ST_WAIT_CFG_ACK; - end else begin - // too many bytes in packet - eth_state <= ST_DISCARD; - end - end else begin - // early tlast means packet too short!! - if (s_axis_tlast) begin - eth_state <= ST_IDLE; - end else begin - cfg_byte_cnt <= cfg_byte_cnt + 4'd1; - end - end - end - end - - ST_WAIT_CFG_ACK: begin - // any incoming packet while waiting ack is discarded - if (cfg_ack_pulse_dac_eth || cfg_ack_pulse_adc_eth) begin - if ((~cfg_wait_dac_ack || cfg_ack_pulse_dac_eth) && - (~cfg_wait_adc_ack || cfg_ack_pulse_adc_eth)) begin - eth_state <= ST_IDLE; - end - end - - if (axis_hs && !s_axis_tlast) begin - eth_state <= ST_DISCARD; - end - end - - ST_DISCARD: begin - if (axis_hs && s_axis_tlast) begin - eth_state <= ST_IDLE; - end - end - - default: begin - eth_state <= ST_IDLE; - end - endcase - end - end - // ETH -> DAC: start/reset event sync (* ASYNC_REG = "TRUE" *) logic start_meta_dac, start_sync_dac; logic start_sync_dac_d;