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chore: generator evolution

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otroubi
2026-05-15 13:36:10 +03:00
parent eacffd44b3
commit 9efbd6586f
4 changed files with 9 additions and 3 deletions
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4
designs/reflectometer_base/reflectometer.sv
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@ -5,6 +5,7 @@ module reflectometer_top #(
parameter int unsigned ADC_DATA_WIDTH = 12, parameter int unsigned ADC_DATA_WIDTH = 12,
parameter PACK_FACTOR = 1, parameter PACK_FACTOR = 1,
parameter PROCESS_MODE = 0, parameter PROCESS_MODE = 0,
parameter ZERO_LEVEL = 8192,
parameter ACCUM_WIDTH = 32, parameter ACCUM_WIDTH = 32,
parameter N_MAX = 4096, parameter N_MAX = 4096,
parameter WINDOW_SIZE = 65, parameter WINDOW_SIZE = 65,
@ -191,7 +192,8 @@ module reflectometer_top #(
//------------------------------------------------------------ //------------------------------------------------------------
generator #( generator #(
.DATA_WIDTH(DAC_DATA_WIDTH) .DATA_WIDTH(DAC_DATA_WIDTH),
.ZERO_LEVEL(ZERO_LEVEL)
) generator_inst ( ) generator_inst (
.clk_in(dac_clk), .clk_in(dac_clk),
.rst(dac_rst), .rst(dac_rst),

2
designs/reflectometer_prototype/prototype.sv
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@ -5,6 +5,7 @@ module prototype_top #(
parameter int unsigned ADC_DATA_WIDTH = 12, parameter int unsigned ADC_DATA_WIDTH = 12,
parameter PACK_FACTOR = 1, parameter PACK_FACTOR = 1,
parameter PROCESS_MODE = 0, parameter PROCESS_MODE = 0,
parameter ZERO_LEVEL = 8192,
parameter ACCUM_WIDTH = 32, parameter ACCUM_WIDTH = 32,
parameter N_MAX = 4096, parameter N_MAX = 4096,
parameter WINDOW_SIZE = 65, parameter WINDOW_SIZE = 65,
@ -131,6 +132,7 @@ module prototype_top #(
.PACK_FACTOR(PACK_FACTOR), .PACK_FACTOR(PACK_FACTOR),
.ACCUM_WIDTH(ACCUM_WIDTH), .ACCUM_WIDTH(ACCUM_WIDTH),
.N_MAX(N_MAX), .N_MAX(N_MAX),
.ZERO_LEVEL(ZERO_LEVEL),
.WINDOW_SIZE(WINDOW_SIZE), .WINDOW_SIZE(WINDOW_SIZE),
.PACKET_SIZE(PACKET_SIZE), .PACKET_SIZE(PACKET_SIZE),
.ADC_DATA_WIDTH(ADC_DATA_WIDTH), .ADC_DATA_WIDTH(ADC_DATA_WIDTH),

5
rtl/generator/src/generator.sv
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@ -3,7 +3,8 @@
module generator module generator
#( #(
parameter DATA_WIDTH = 14 parameter DATA_WIDTH = 14,
parameter ZERO_LEVEL = 8192 // 8192 or 0
) )
( (
input clk_in, input clk_in,
@ -78,7 +79,7 @@ module generator
if (cnt_period <= pulse_width_reg) begin if (cnt_period <= pulse_width_reg) begin
pulse_height_out_reg <= pulse_height_reg; pulse_height_out_reg <= pulse_height_reg;
end else begin end else begin
pulse_height_out_reg <= '0; pulse_height_out_reg <= ZERO_LEVEL;
end end
if (cnt_period == pulse_period_reg) begin if (cnt_period == pulse_period_reg) begin
cnt_period <= 0; cnt_period <= 0;

1
rtl/generator/tests/generator_tb.sv
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@ -3,6 +3,7 @@
module generator_tb; module generator_tb;
parameter DATA_WIDTH = 14; parameter DATA_WIDTH = 14;
parameter ZERO_LEVEL = 8192;
parameter CLK_PERIOD = 16; parameter CLK_PERIOD = 16;
logic clk; logic clk;