From 9efbd6586fe229cd338ea4accf3cbddc8f730ec2 Mon Sep 17 00:00:00 2001 From: otroubi Date: Fri, 15 May 2026 13:36:10 +0300 Subject: [PATCH] chore: generator evolution --- designs/reflectometer_base/reflectometer.sv | 4 +++- designs/reflectometer_prototype/prototype.sv | 2 ++ rtl/generator/src/generator.sv | 5 +++-- rtl/generator/tests/generator_tb.sv | 1 + 4 files changed, 9 insertions(+), 3 deletions(-) diff --git a/designs/reflectometer_base/reflectometer.sv b/designs/reflectometer_base/reflectometer.sv index 68f729c..295004d 100644 --- a/designs/reflectometer_base/reflectometer.sv +++ b/designs/reflectometer_base/reflectometer.sv @@ -5,6 +5,7 @@ module reflectometer_top #( parameter int unsigned ADC_DATA_WIDTH = 12, parameter PACK_FACTOR = 1, parameter PROCESS_MODE = 0, + parameter ZERO_LEVEL = 8192, parameter ACCUM_WIDTH = 32, parameter N_MAX = 4096, parameter WINDOW_SIZE = 65, @@ -191,7 +192,8 @@ module reflectometer_top #( //------------------------------------------------------------ generator #( - .DATA_WIDTH(DAC_DATA_WIDTH) + .DATA_WIDTH(DAC_DATA_WIDTH), + .ZERO_LEVEL(ZERO_LEVEL) ) generator_inst ( .clk_in(dac_clk), .rst(dac_rst), diff --git a/designs/reflectometer_prototype/prototype.sv b/designs/reflectometer_prototype/prototype.sv index 6470abf..7ad51ac 100644 --- a/designs/reflectometer_prototype/prototype.sv +++ b/designs/reflectometer_prototype/prototype.sv @@ -5,6 +5,7 @@ module prototype_top #( parameter int unsigned ADC_DATA_WIDTH = 12, parameter PACK_FACTOR = 1, parameter PROCESS_MODE = 0, + parameter ZERO_LEVEL = 8192, parameter ACCUM_WIDTH = 32, parameter N_MAX = 4096, parameter WINDOW_SIZE = 65, @@ -131,6 +132,7 @@ module prototype_top #( .PACK_FACTOR(PACK_FACTOR), .ACCUM_WIDTH(ACCUM_WIDTH), .N_MAX(N_MAX), + .ZERO_LEVEL(ZERO_LEVEL), .WINDOW_SIZE(WINDOW_SIZE), .PACKET_SIZE(PACKET_SIZE), .ADC_DATA_WIDTH(ADC_DATA_WIDTH), diff --git a/rtl/generator/src/generator.sv b/rtl/generator/src/generator.sv index 82d0457..89aab4a 100644 --- a/rtl/generator/src/generator.sv +++ b/rtl/generator/src/generator.sv @@ -3,7 +3,8 @@ module generator #( - parameter DATA_WIDTH = 14 + parameter DATA_WIDTH = 14, + parameter ZERO_LEVEL = 8192 // 8192 or 0 ) ( input clk_in, @@ -78,7 +79,7 @@ module generator if (cnt_period <= pulse_width_reg) begin pulse_height_out_reg <= pulse_height_reg; end else begin - pulse_height_out_reg <= '0; + pulse_height_out_reg <= ZERO_LEVEL; end if (cnt_period == pulse_period_reg) begin cnt_period <= 0; diff --git a/rtl/generator/tests/generator_tb.sv b/rtl/generator/tests/generator_tb.sv index 4d4cef9..55e51f6 100644 --- a/rtl/generator/tests/generator_tb.sv +++ b/rtl/generator/tests/generator_tb.sv @@ -3,6 +3,7 @@ module generator_tb; parameter DATA_WIDTH = 14; + parameter ZERO_LEVEL = 8192; parameter CLK_PERIOD = 16; logic clk;