working generator and simple tb

rtl/generator/tests/generator_tb.sv

@@ -15,26 +15,27 @@ module generator_tb;
     logic [DATA_WIDTH-1:0] pulse_height;
     logic [15:0] pulse_num;
 
-    logic pulse;
-    logic [DATA_WIDTH-1:0] pulse_height_out;
-    logic sample_done, sample_req;
+    wire pulse;
+    wire [DATA_WIDTH-1:0] dac_out;
+    wire sample_done;
+    logic sample_req;
 
     // DUT
     generator #(
         .DATA_WIDTH(DATA_WIDTH),
         .ZERO_LEVEL(ZERO_LEVEL)
     ) dut (
-        .clk_in(clk),
+        .clk_dac(clk),
         .rst(rst),
         .start(start),
         .pulse_width(pulse_width),
         .pulse_period(pulse_period),
         .pulse_height(pulse_height),
         .pulse_num(pulse_num),
-        .pulse(pulse),
-        .pulse_height_out(pulse_height_out),
-        .sample_done(sample_done),
-        .sample_req(sample_req)
+        .dac_wrt(pulse),
+        .dac_out(dac_out),
+        .done(sample_done),
+        .request(sample_req)
     );
 
     // Clock
@@ -53,33 +54,33 @@ module generator_tb;
         pulse_period = 0;
         pulse_height = 0;
         pulse_num    = 0;
-        sample_done  = 0;
+        sample_req   = 0;
 
         repeat(5) @(posedge clk);
         rst = 0;
 
-        // --- Test 1 ---
-        // 3 clk 1, 5 clk 0,  4 pulses
        repeat(2) @(posedge clk);
-        pulse_width  = 1;
+        pulse_width  = 0;
         pulse_period = 20;
         pulse_num    = 4;
-        pulse_height = 14'h3FF;
+        pulse_height = 1024;
+
+        // startup signal
         #1;
         start = 1;
-
-        repeat(1) @(posedge clk);
-        start = 0;
-
-        wait(sample_req == 1);
         @(posedge clk);
         #1;
-        sample_done = 1;
-        wait(sample_req == 0)
-            sample_done = 0;
+        start = 0;
 
-        repeat(pulse_period*pulse_num+10) @(posedge clk);
-    
+        repeat(pulse_num) begin
+            // syncronization
+            wait(sample_done == 1);
+            repeat(4) @(posedge clk);
+            sample_req = 1;
+            repeat(2) @(posedge clk);
+            sample_req = 0;
+        end
+        wait(sample_done == 1);
     //     // --- Test 2 ---
     //     $display("\n--- SECOND RUN ---\n");
 
@@ -115,8 +116,9 @@ module generator_tb;
 
 
     //     $display("\n=== TEST FINISHED ===");
-    //     $finish;
-     end
+    #100;
+    $finish;
+    end
 
     // // Display
     // always @(posedge clk) begin