diff --git a/rtl/generator/src/generator.sv b/rtl/generator/src/generator.sv
index fd5cb7d..52051a2 100644
--- a/rtl/generator/src/generator.sv
+++ b/rtl/generator/src/generator.sv
@@ -26,7 +26,7 @@ module generator
     logic [15:0] cnt_pulse_num;
     logic [31:0] cnt_pulse_period;
 
-    logic enable;
+    logic enable, synced;
 
     always @(posedge clk_dac) begin
         if (rst) begin
@@ -39,52 +39,47 @@ module generator
             dac_out            <=  ZERO_LEVEL;
             done               <=  0;
             enable             <=  0;
+            synced             <=  0;
         end 
         else begin
+            // wait start for updating registers
             if (start & !enable) begin
-                enable <= 1;
-
-                sample_req <= 1;
-                
-                pulse_width_reg <= pulse_width;
-                pulse_period_reg <= pulse_period;
-                pulse_num_reg <= pulse_num;
-                pulse_height_reg <= pulse_height;
-            end 
+                enable              <= 1;
+                pulse_width_reg     <= pulse_width;
+                pulse_period_reg    <= pulse_period;
+                pulse_num_reg       <= pulse_num;
+                pulse_height_reg    <= pulse_height;
+            end
+            // main work cycle
             if (enable) begin
-
-                if (!sample_req && (cnt_period == 0)) begin
-                    pulse_height_out_reg <= ZERO_LEVEL;
-                    if (sample_done) begin
-                        sample_req <= 1'b0;
-                    end
-                    
-                    if (!sample_done) begin
-                        if (cnt_pulse_num == pulse_num_reg - 1) begin
-                            enable <= 1'b0;
+                if (cnt_pulse_num != pulse_num_reg) begin
+                    // wait for synchronization with sampler
+                    if (!synced) begin
+                        done <= 1;
+                        if (request) begin
+                            synced  <= 1;
+                            done    <= 0;
                         end
-                        else begin
-                            cnt_pulse_num <= cnt_pulse_num + 1;
-                            sample_req <= 1'b1;
-                            cnt_period <= 1;
+                    end
+                    else begin
+                        if (cnt_pulse_period != pulse_period_reg) begin
+                            if (cnt_pulse_period < pulse_width_reg)
+                                dac_out <= pulse_height_reg;
+                            else
+                                dac_out <= ZERO_LEVEL;
+                            cnt_pulse_period <= cnt_pulse_period + 1;
+                        end
+                        else if (cnt_pulse_period == pulse_period_reg) begin
+                            cnt_pulse_num       <=  cnt_pulse_num + 1;
+                            cnt_pulse_period    <=  0;
+                            synced              <=  0;
+                            dac_out             <=  ZERO_LEVEL;
                         end
                     end
                 end
-                 else begin
-                        
-                    if (cnt_period < pulse_width_reg - 1) begin
-                        pulse_height_out_reg <= pulse_height_reg;
-                    end else begin
-                        pulse_height_out_reg <= ZERO_LEVEL;
-                    end
-                    if (cnt_period == pulse_period_reg - 1) begin
-                        cnt_period <= 0;
-                    end else begin
-                        cnt_period <= cnt_period + 1;
-                    end
-                    if (sample_req && sample_done) begin
-                        sample_req <= 0;
-                    end
+                else if (cnt_pulse_num == pulse_num_reg) begin
+                    cnt_pulse_num   <=  0;
+                    enable          <=  0;
                 end
             end
         end
@@ -92,8 +87,8 @@ module generator
 
     // Gated DAC write signal from DAC clock. Needed for posedge
     OBUF OBUF_pulse_clk (
-        .I(clk_in & enable),
-        .O(pulse)
+        .I(clk_dac & enable),
+        .O(dac_wrt)
     );
     
 endmodule
diff --git a/rtl/generator/tests/generator_tb.sv b/rtl/generator/tests/generator_tb.sv
index 451ffce..3512745 100644
--- a/rtl/generator/tests/generator_tb.sv
+++ b/rtl/generator/tests/generator_tb.sv
@@ -15,26 +15,27 @@ module generator_tb;
     logic [DATA_WIDTH-1:0] pulse_height;
     logic [15:0] pulse_num;
 
-    logic pulse;
-    logic [DATA_WIDTH-1:0] pulse_height_out;
-    logic sample_done, sample_req;
+    wire pulse;
+    wire [DATA_WIDTH-1:0] dac_out;
+    wire sample_done;
+    logic sample_req;
 
     // DUT
     generator #(
         .DATA_WIDTH(DATA_WIDTH),
         .ZERO_LEVEL(ZERO_LEVEL)
     ) dut (
-        .clk_in(clk),
+        .clk_dac(clk),
         .rst(rst),
         .start(start),
         .pulse_width(pulse_width),
         .pulse_period(pulse_period),
         .pulse_height(pulse_height),
         .pulse_num(pulse_num),
-        .pulse(pulse),
-        .pulse_height_out(pulse_height_out),
-        .sample_done(sample_done),
-        .sample_req(sample_req)
+        .dac_wrt(pulse),
+        .dac_out(dac_out),
+        .done(sample_done),
+        .request(sample_req)
     );
 
     // Clock
@@ -53,33 +54,33 @@ module generator_tb;
         pulse_period = 0;
         pulse_height = 0;
         pulse_num    = 0;
-        sample_done  = 0;
+        sample_req   = 0;
 
         repeat(5) @(posedge clk);
         rst = 0;
 
-        // --- Test 1 ---
-        // 3 clk 1, 5 clk 0,  4 pulses
        repeat(2) @(posedge clk);
-        pulse_width  = 1;
+        pulse_width  = 0;
         pulse_period = 20;
         pulse_num    = 4;
-        pulse_height = 14'h3FF;
+        pulse_height = 1024;
+
+        // startup signal
         #1;
         start = 1;
-
-        repeat(1) @(posedge clk);
-        start = 0;
-
-        wait(sample_req == 1);
         @(posedge clk);
         #1;
-        sample_done = 1;
-        wait(sample_req == 0)
-            sample_done = 0;
+        start = 0;
 
-        repeat(pulse_period*pulse_num+10) @(posedge clk);
-    
+        repeat(pulse_num) begin
+            // syncronization
+            wait(sample_done == 1);
+            repeat(4) @(posedge clk);
+            sample_req = 1;
+            repeat(2) @(posedge clk);
+            sample_req = 0;
+        end
+        wait(sample_done == 1);
     //     // --- Test 2 ---
     //     $display("\n--- SECOND RUN ---\n");
 
@@ -115,8 +116,9 @@ module generator_tb;
 
 
     //     $display("\n=== TEST FINISHED ===");
-    //     $finish;
-     end
+    #100;
+    $finish;
+    end
 
     // // Display
     // always @(posedge clk) begin