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working generator and simple tb

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This commit is contained in:
Zer0Nu11
2026-06-09 13:08:51 +03:00
parent c8e11a2a1f
commit 9c74fe91e8
2 changed files with 63 additions and 66 deletions
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77
rtl/generator/src/generator.sv
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@ -26,7 +26,7 @@ module generator
logic [15:0] cnt_pulse_num;
logic [31:0] cnt_pulse_period;
logic enable;
logic enable, synced;
always @(posedge clk_dac) begin
if (rst) begin
@ -39,52 +39,47 @@ module generator
dac_out <= ZERO_LEVEL;
done <= 0;
enable <= 0;
synced <= 0;
end
else begin
// wait start for updating registers
if (start & !enable) begin
enable <= 1;
sample_req <= 1;
pulse_width_reg <= pulse_width;
pulse_period_reg <= pulse_period;
pulse_num_reg <= pulse_num;
pulse_height_reg <= pulse_height;
end
enable <= 1;
pulse_width_reg <= pulse_width;
pulse_period_reg <= pulse_period;
pulse_num_reg <= pulse_num;
pulse_height_reg <= pulse_height;
end
// main work cycle
if (enable) begin
if (!sample_req && (cnt_period == 0)) begin
pulse_height_out_reg <= ZERO_LEVEL;
if (sample_done) begin
sample_req <= 1'b0;
end
if (!sample_done) begin
if (cnt_pulse_num == pulse_num_reg - 1) begin
enable <= 1'b0;
if (cnt_pulse_num != pulse_num_reg) begin
// wait for synchronization with sampler
if (!synced) begin
done <= 1;
if (request) begin
synced <= 1;
done <= 0;
end
else begin
cnt_pulse_num <= cnt_pulse_num + 1;
sample_req <= 1'b1;
cnt_period <= 1;
end
else begin
if (cnt_pulse_period != pulse_period_reg) begin
if (cnt_pulse_period < pulse_width_reg)
dac_out <= pulse_height_reg;
else
dac_out <= ZERO_LEVEL;
cnt_pulse_period <= cnt_pulse_period + 1;
end
else if (cnt_pulse_period == pulse_period_reg) begin
cnt_pulse_num <= cnt_pulse_num + 1;
cnt_pulse_period <= 0;
synced <= 0;
dac_out <= ZERO_LEVEL;
end
end
end
else begin
if (cnt_period < pulse_width_reg - 1) begin
pulse_height_out_reg <= pulse_height_reg;
end else begin
pulse_height_out_reg <= ZERO_LEVEL;
end
if (cnt_period == pulse_period_reg - 1) begin
cnt_period <= 0;
end else begin
cnt_period <= cnt_period + 1;
end
if (sample_req && sample_done) begin
sample_req <= 0;
end
else if (cnt_pulse_num == pulse_num_reg) begin
cnt_pulse_num <= 0;
enable <= 0;
end
end
end
@ -92,8 +87,8 @@ module generator
// Gated DAC write signal from DAC clock. Needed for posedge
OBUF OBUF_pulse_clk (
.I(clk_in & enable),
.O(pulse)
.I(clk_dac & enable),
.O(dac_wrt)
);
endmodule