dma ram test

2026-07-27 19:24:47 +03:00
parent ee83bcbb9e
commit 95540713e0
4 changed files with 33 additions and 364 deletions
@@ -14,6 +14,8 @@ VERILOG_SOURCES += $(LIBS_DIR)/axi/axi_reg/axi4l_reg_map.sv
 VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_rd.v
 VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_wr.v
 VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma.v
+VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_ram.v
+VERILOG_SOURCES += $(RTL_DIR)/axi_ram_wrapper.sv
 VERILOG_SOURCES += $(RTL_DIR)/controller.sv
 VERILOG_SOURCES += $(RTL_DIR)/dma_controller.sv
 VERILOG_SOURCES += $(RTL_DIR)/shaper_axis_desc.sv