diff --git a/designs/controller_dma_connective/tests/Makefile b/designs/controller_dma_connective/tests/Makefile index 7bd46ca..3dc8182 100644 --- a/designs/controller_dma_connective/tests/Makefile +++ b/designs/controller_dma_connective/tests/Makefile @@ -14,6 +14,8 @@ VERILOG_SOURCES += $(LIBS_DIR)/axi/axi_reg/axi4l_reg_map.sv VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_rd.v VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_wr.v VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma.v +VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_ram.v +VERILOG_SOURCES += $(RTL_DIR)/axi_ram_wrapper.sv VERILOG_SOURCES += $(RTL_DIR)/controller.sv VERILOG_SOURCES += $(RTL_DIR)/dma_controller.sv VERILOG_SOURCES += $(RTL_DIR)/shaper_axis_desc.sv diff --git a/designs/controller_dma_connective/tests/tb_control_dma_behav.wcfg b/designs/controller_dma_connective/tests/tb_control_dma_behav.wcfg deleted file mode 100644 index 16048c6..0000000 --- a/designs/controller_dma_connective/tests/tb_control_dma_behav.wcfg +++ /dev/null @@ -1,236 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - dac_clk_in - dac_clk_in - #FFA500 - true - - - adc_clk_in - adc_clk_in - - - rst_n - rst_n - #800080 - true - - - rst_soft - rst_soft - #008080 - true - - - start - start - #E0FFFF - true - - - adc_start_pulse - adc_start_pulse - - - dac_start_pulse - dac_start_pulse - - - busy - busy - #E0FFFF - true - - - finish - finish - #FAAFBE - true - - - finish_pulse - finish_pulse - - - cfg_bus_valid - cfg_bus_valid - #FF0080 - true - - - cfg_bus_input[159:0] - cfg_bus_input[159:0] - #FF0080 - true - - - dac_pulse_width[31:0] - dac_pulse_width[31:0] - #FFA500 - true - - - dac_pulse_period[31:0] - dac_pulse_period[31:0] - #FFA500 - true - - - dac_pulse_height[11:0] - dac_pulse_height[11:0] - #FFA500 - true - HEXRADIX - - - dac_pulse_num[15:0] - dac_pulse_num[15:0] - #FFA500 - true - - - adc_pulse_period[31:0] - adc_pulse_period[31:0] - #FFA500 - true - - - adc_pulse_num[15:0] - adc_pulse_num[15:0] - #FFA500 - true - - - adc_window_size[31:0] - adc_window_size[31:0] - - - dac_start - dac_start - #FFA500 - true - - - adc_start - adc_start - - - dac_rst - dac_rst - #FFA500 - true - - - adc_rst - adc_rst - - - tb signals - label - - dac_rst_count[31:0] - dac_rst_count[31:0] - #F0E68C - true - - - adc_rst_count[31:0] - adc_rst_count[31:0] - #F0E68C - true - - - dac_start_count[31:0] - dac_start_count[31:0] - #F0E68C - true - - - adc_start_count[31:0] - adc_start_count[31:0] - #F0E68C - true - - - - cfg_req_toggle_adc - cfg_req_toggle_adc - #FFFF00 - true - - - cfg_req_toggle_dac - cfg_req_toggle_dac - #FFFF00 - true - - - cfg_ack_toggle_adc - cfg_ack_toggle_adc - #FF00FF - true - - - cfg_ack_toggle_dac - cfg_ack_toggle_dac - #FF00FF - true - - - cfg_wait_adc_ack - cfg_wait_adc_ack - #0000FF - true - - - cfg_wait_dac_ack - cfg_wait_dac_ack - #0000FF - true - - - cfg_req_pulse_adc - cfg_req_pulse_adc - #808000 - true - - - cfg_req_pulse_dac - cfg_req_pulse_dac - #808000 - true - - - cfg_ack_pulse_adc - cfg_ack_pulse_adc - #DCDCDC - true - - - cfg_ack_pulse_dac - cfg_ack_pulse_dac - #DCDCDC - true - - diff --git a/designs/controller_dma_connective/tests/tb_controller_dma_wrapper_axil.sv b/designs/controller_dma_connective/tests/tb_controller_dma_wrapper_axil.sv index 176b40b..76c2cac 100644 --- a/designs/controller_dma_connective/tests/tb_controller_dma_wrapper_axil.sv +++ b/designs/controller_dma_connective/tests/tb_controller_dma_wrapper_axil.sv @@ -238,79 +238,6 @@ axis_flat_to_if #( .m_axis(dma_write_data) ); -// AXI4 MASTER DMA - -axi4_if #( - .ADDR_W(dma_reg_pkg::AXI_ADDR_WIDTH), - .DATA_W(AXI_DATA_WIDTH), - .ID_W (AXI_ID_WIDTH), - .USER_W(AXI_USER_WIDTH) -) m_axi ( - .aclk(ctrl_clk), - .aresetn(rst_n) -); - -logic [AXI_USER_WIDTH-1:0] unused_awuser; -logic [AXI_USER_WIDTH-1:0] unused_wuser; -logic [AXI_USER_WIDTH-1:0] unused_aruser; - -axi4_if_to_flat #( - .ADDR_W (dma_reg_pkg::AXI_ADDR_WIDTH), - .DATA_W (AXI_DATA_WIDTH), - .ID_W (AXI_ID_WIDTH), - .USER_W (AXI_USER_WIDTH) -) u_axi_if_to_flat ( - .s_axi(m_axi), - - .m_axi_awid (m_axi_awid), - .m_axi_awaddr (m_axi_awaddr), - .m_axi_awlen (m_axi_awlen), - .m_axi_awsize (m_axi_awsize), - .m_axi_awburst (m_axi_awburst), - .m_axi_awlock (m_axi_awlock), - .m_axi_awcache (m_axi_awcache), - .m_axi_awprot (m_axi_awprot), - .m_axi_awqos (), - .m_axi_awregion(), - .m_axi_awuser (unused_awuser), - .m_axi_awvalid (m_axi_awvalid), - .m_axi_awready (m_axi_awready), - - .m_axi_wdata (m_axi_wdata), - .m_axi_wstrb (m_axi_wstrb), - .m_axi_wlast (m_axi_wlast), - .m_axi_wuser (unused_wuser), - .m_axi_wvalid (m_axi_wvalid), - .m_axi_wready (m_axi_wready), - - .m_axi_bid (m_axi_bid), - .m_axi_bresp (m_axi_bresp), - .m_axi_buser ({AXI_USER_WIDTH{1'b0}}), - .m_axi_bvalid (m_axi_bvalid), - .m_axi_bready (m_axi_bready), - - .m_axi_arid (m_axi_arid), - .m_axi_araddr (m_axi_araddr), - .m_axi_arlen (m_axi_arlen), - .m_axi_arsize (m_axi_arsize), - .m_axi_arburst (m_axi_arburst), - .m_axi_arlock (m_axi_arlock), - .m_axi_arcache (m_axi_arcache), - .m_axi_arprot (m_axi_arprot), - .m_axi_arqos (), - .m_axi_arregion(), - .m_axi_aruser (unused_aruser), - .m_axi_arvalid (m_axi_arvalid), - .m_axi_arready (m_axi_arready), - - .m_axi_rid (m_axi_rid), - .m_axi_rdata (m_axi_rdata), - .m_axi_rresp (m_axi_rresp), - .m_axi_rlast (m_axi_rlast), - .m_axi_ruser ({AXI_USER_WIDTH{1'b0}}), - .m_axi_rvalid (m_axi_rvalid), - .m_axi_rready (m_axi_rready) -); // Controller ADC/DAC outputs. @@ -365,9 +292,7 @@ axi4_if_to_flat #( .adc_rst(adc_rst), .m_axis_read_data(dma_read_data), - .s_axis_write_data(dma_write_data), - - .m_axi(m_axi) + .s_axis_write_data(dma_write_data) ); endmodule : tb_controller_wrapper_axil diff --git a/designs/controller_dma_connective/tests/test_controller_and_dma.py b/designs/controller_dma_connective/tests/test_controller_and_dma.py index b25c982..bb6ed98 100644 --- a/designs/controller_dma_connective/tests/test_controller_and_dma.py +++ b/designs/controller_dma_connective/tests/test_controller_and_dma.py @@ -1,9 +1,8 @@ import cocotb from cocotb.clock import Clock -from cocotb.handle import Immediate from cocotb.triggers import RisingEdge from cocotbext.axi import AxiLiteBus, AxiLiteMaster -from cocotbext.axi import AxiBus, AxiRam, AxiStreamBus, AxiStreamSource, AxiStreamSink +from cocotbext.axi import AxiBus, AxiRam, AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame # Register indexes from axi4l_reg_map_controller_pkg.sv @@ -140,77 +139,56 @@ async def simple_controller_start_check(dut): await RisingEdge(dut.dac_start) @cocotb.test() -async def test_dma_write(dut): +async def simple_dma_mem_to_mem(dut): tb = TB(dut) await tb.reset() - data = bytes(range(64)) + SRC_ADDR = 0x1000 + LENGTH = 8 - #write data into memory + tx_data = bytes([ 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88 ]) - await tb.write_reg(REG_DESC_WRITE_ADDR, 0x1000) - await tb.write_reg(REG_DESC_WRITE_LEN_AND_TAG, 64) + ## write part + await tb.write_reg(REG_DESC_WRITE_ADDR, SRC_ADDR) + await tb.write_reg(REG_DESC_WRITE_LEN_AND_TAG, LENGTH) await tb.write_reg(REG_CONTROL, 1 << CTRL_SEND_DESC_WRITE) - await RisingEdge(dut.ctrl_clk) - cocotb.start_soon(tb.axis_source.send(data)) - for _ in range(200): - await tb.write_reg( REG_CONTROL, 1 << CTRL_TAKE_STATUS_WRITE) + await tb.axis_source.send(AxiStreamFrame(tx_data)) + for _ in range(20): await RisingEdge(dut.ctrl_clk) - status = await tb.read_reg( REG_STATUS_WRITE_LEN) - if status == 64: - break + await tb.write_reg(REG_CONTROL, 1 << CTRL_TAKE_STATUS_WRITE) + + for _ in range(10): + await RisingEdge(dut.ctrl_clk) - else: - assert False, "DMA timeout" + assert await tb.read_reg(REG_STATUS_WRITE_CONFIG) == 0 + assert await tb.read_reg(REG_STATUS_WRITE_LEN) == 0x8 - mem = await tb.mem.read( 0x1000, 64) - assert mem == data + ## read part -@cocotb.test() -async def test_dma_read(dut): - tb = TB(dut) - await tb.reset() + await tb.write_reg(REG_DESC_READ_ADDR, SRC_ADDR) + await tb.write_reg(REG_DESC_READ_LEN, LENGTH) + await tb.write_reg(REG_DESC_READ_CONFIG, 0x0000_0001) - data = bytes(range(64)) + await tb.write_reg(REG_CONTROL, 1 << CTRL_SEND_DESC_READ) - #read data from memory + rx_frame = await tb.axis_sink.recv() - await tb.mem.write( 0x2000, data) - - await tb.write_reg( REG_DESC_READ_ADDR, 0x2000) - await tb.write_reg( REG_DESC_READ_LEN, 64) - await tb.write_reg( REG_DESC_READ_CONFIG, 1) - - await tb.write_reg( REG_CONTROL, 1 << CTRL_SEND_DESC_READ) - - frame = await tb.axis_sink.recv() - assert frame.data == data - - await tb.write_reg( - REG_CONTROL, - 1 << CTRL_TAKE_STATUS_READ - ) - - for _ in range(100): - - status = await tb.read_reg( - REG_READ_STATUS - ) - - if status != 0: - break + for _ in range(20): + await RisingEdge(dut.ctrl_clk) + await tb.write_reg(REG_CONTROL, 1 << CTRL_TAKE_STATUS_READ) + + for _ in range(10): await RisingEdge(dut.ctrl_clk) - else: - assert False, "DMA read status timeout" + + assert await tb.read_reg(REG_READ_STATUS) == 0x1 - - + assert bytes(rx_frame) == tx_data