fix: incorrect fifo threshold value

2026-04-17 21:58:20 +03:00
parent 7f9ad95e68
commit 8e46f965df
1 changed files with 1 additions and 1 deletions
--- a/rtl/accum/src/out_axis_fifo.sv
+++ b/rtl/accum/src/out_axis_fifo.sv
@ -143,7 +143,7 @@ module out_axis_fifo #(
      .FIFO_WRITE_DEPTH(FIFO_WDEPTH), 
      .FULL_RESET_VALUE(0),
      .PROG_EMPTY_THRESH(PACKET_SIZE),
-      .PROG_FULL_THRESH(PACKET_SIZE),
+      .PROG_FULL_THRESH(PACKET_SIZE / (ACCUM_WIDTH / 8)),
      .RD_DATA_COUNT_WIDTH(RDEPTH_BITS),    
      .READ_DATA_WIDTH(8),           // always 8 bit for eth
      .READ_MODE("fwft"),