baulin.fa/reflectometer_fpga_project
1
0
Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity

rtl: reflectometer add synchronizer logic

Browse Source
This commit is contained in:
otroubi
2026-05-06 15:38:25 +03:00
parent c279f1158d
commit 8c4154baf0
1 changed files with 54 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

56
designs/reflectometer/reflectometer.sv
View File

@ -269,6 +269,53 @@ module reflectometer_top #(
// -------------------------------------------------------------------------
// DAC
// -------------------------------------------------------------------------
(* MARK_DEBUG="true" *) logic sample_req;
(* MARK_DEBUG="true" *) logic sample_req_sync1;
(* MARK_DEBUG="true" *) logic sample_req_sync2;
(* MARK_DEBUG="true" *) logic sample_req_sync3;
(* MARK_DEBUG="true" *) logic sample_done;
(* MARK_DEBUG="true" *) logic sample_done_sync1;
(* MARK_DEBUG="true" *) logic sample_done_sync2;
(* MARK_DEBUG="true" *) logic sample_done_sync3;
//------------------------------------------------------------
// DAC -> ADC CDC
//------------------------------------------------------------
always_ff @(posedge adc_clk_in or posedge adc_rst) begin
if (adc_rst) begin
sample_req <= 1'b0;
sample_req_sync2 <= 1'b0;
sample_req_sync3 <= 1'b0;
end
else begin
sample_req_sync2 <= sample_req_sync1;
sample_req_sync3 <= sample_req_sync2;
sample_req <= sample_req_sync3;
end
end
//------------------------------------------------------------
// ADC -> DAC CDC
//------------------------------------------------------------
always_ff @(posedge dac_clk_in or posedge dac_rst) begin
if (dac_rst) begin
sample_done <= 1'b0;
sample_done_sync2 <= 1'b0;
sample_done_sync3 <= 1'b0;
end
else begin
sample_done_sync2 <= sample_done_sync1;
sample_done_sync3 <= sample_done_sync2;
sample_done <= sample_done_sync3;
end
end
//------------------------------------------------------------
// Generator
//------------------------------------------------------------
generator #(
.DATA_WIDTH(DAC_DATA_WIDTH)
) generator_inst (
@ -280,7 +327,9 @@ module reflectometer_top #(
.pulse_height(dac_pulse_height),
.pulse_num(dac_pulse_num),
.pulse(p2_wrt),
.pulse_height_out(p2_data)
.pulse_height_out(p2_data),
.sample_done(sample_done),
.sample_req(sample_req_sync1)
);
// adc clk mgt
@ -325,7 +374,10 @@ module reflectometer_top #(
.data_in(ch2_data),
.out_of_range(ch2_otr),
.m_axis_tdata(accum_m_axis_tdata),
.m_axis_tvalid(acum_m_axis_tvalid)
.m_axis_tvalid(acum_m_axis_tvalid),
.smp_num(adc_pulse_period),
.sample_req(sample_req),
.sample_done(sample_done_sync1)
);
// -------------------------------------------------------------------------