From 8c4154baf0eeec8f259f44592da6a3e3420b8dda Mon Sep 17 00:00:00 2001 From: otroubi Date: Wed, 6 May 2026 15:38:25 +0300 Subject: [PATCH] rtl: reflectometer add synchronizer logic --- designs/reflectometer/reflectometer.sv | 56 +++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 2 deletions(-) diff --git a/designs/reflectometer/reflectometer.sv b/designs/reflectometer/reflectometer.sv index b36f39c..61d13da 100644 --- a/designs/reflectometer/reflectometer.sv +++ b/designs/reflectometer/reflectometer.sv @@ -269,6 +269,53 @@ module reflectometer_top #( // ------------------------------------------------------------------------- // DAC // ------------------------------------------------------------------------- + + (* MARK_DEBUG="true" *) logic sample_req; + (* MARK_DEBUG="true" *) logic sample_req_sync1; + (* MARK_DEBUG="true" *) logic sample_req_sync2; + (* MARK_DEBUG="true" *) logic sample_req_sync3; + + (* MARK_DEBUG="true" *) logic sample_done; + (* MARK_DEBUG="true" *) logic sample_done_sync1; + (* MARK_DEBUG="true" *) logic sample_done_sync2; + (* MARK_DEBUG="true" *) logic sample_done_sync3; + + //------------------------------------------------------------ + // DAC -> ADC CDC + //------------------------------------------------------------ + always_ff @(posedge adc_clk_in or posedge adc_rst) begin + if (adc_rst) begin + sample_req <= 1'b0; + sample_req_sync2 <= 1'b0; + sample_req_sync3 <= 1'b0; + end + else begin + sample_req_sync2 <= sample_req_sync1; + sample_req_sync3 <= sample_req_sync2; + sample_req <= sample_req_sync3; + end + end + + //------------------------------------------------------------ + // ADC -> DAC CDC + //------------------------------------------------------------ + always_ff @(posedge dac_clk_in or posedge dac_rst) begin + if (dac_rst) begin + sample_done <= 1'b0; + sample_done_sync2 <= 1'b0; + sample_done_sync3 <= 1'b0; + end + else begin + sample_done_sync2 <= sample_done_sync1; + sample_done_sync3 <= sample_done_sync2; + sample_done <= sample_done_sync3; + end + end + + //------------------------------------------------------------ + // Generator + //------------------------------------------------------------ + generator #( .DATA_WIDTH(DAC_DATA_WIDTH) ) generator_inst ( @@ -280,7 +327,9 @@ module reflectometer_top #( .pulse_height(dac_pulse_height), .pulse_num(dac_pulse_num), .pulse(p2_wrt), - .pulse_height_out(p2_data) + .pulse_height_out(p2_data), + .sample_done(sample_done), + .sample_req(sample_req_sync1) ); // adc clk mgt @@ -325,7 +374,10 @@ module reflectometer_top #( .data_in(ch2_data), .out_of_range(ch2_otr), .m_axis_tdata(accum_m_axis_tdata), - .m_axis_tvalid(acum_m_axis_tvalid) + .m_axis_tvalid(acum_m_axis_tvalid), + .smp_num(adc_pulse_period), + .sample_req(sample_req), + .sample_done(sample_done_sync1) ); // -------------------------------------------------------------------------