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fix: signal in axis_mac

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Phil
2026-04-14 12:32:10 +03:00
parent 1c654f4e8e
commit 8907fea8a4
1 changed files with 2 additions and 2 deletions
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4
rtl/ethernet-udp/src/eth/axis_mac.sv
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@ -18,7 +18,7 @@ module axis_mac
(* MARK_DEBUG="true" *)output reg m_axis_rx_tvalid,
(* MARK_DEBUG="true" *)input wire m_axis_rx_tready,
(* MARK_DEBUG="true" *)output reg m_axis_rx_tlast,
(* MARK_DEBUG="true" *)output [15:0] udp_rec_data_length,
(* MARK_DEBUG="true" *)output wire [15:0] udp_rec_data_length,
// tx part
(* MARK_DEBUG="true" *)input wire send_req,
@ -81,7 +81,7 @@ module axis_mac
// RX signals
reg [10:0] udp_rec_ram_read_addr;
wire [7:0] udp_rec_ram_rdata;
wire [15:0] udp_rec_data_length;
wire udp_rec_data_valid;
mac_top mac_top0 (