From 8907fea8a44ee50a919dca9f6c2cba249805e2ff Mon Sep 17 00:00:00 2001 From: Phil Date: Tue, 14 Apr 2026 12:32:10 +0300 Subject: [PATCH] fix: signal in axis_mac --- rtl/ethernet-udp/src/eth/axis_mac.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/rtl/ethernet-udp/src/eth/axis_mac.sv b/rtl/ethernet-udp/src/eth/axis_mac.sv index 87bb56a..084f200 100644 --- a/rtl/ethernet-udp/src/eth/axis_mac.sv +++ b/rtl/ethernet-udp/src/eth/axis_mac.sv @@ -18,7 +18,7 @@ module axis_mac (* MARK_DEBUG="true" *)output reg m_axis_rx_tvalid, (* MARK_DEBUG="true" *)input wire m_axis_rx_tready, (* MARK_DEBUG="true" *)output reg m_axis_rx_tlast, - (* MARK_DEBUG="true" *)output [15:0] udp_rec_data_length, + (* MARK_DEBUG="true" *)output wire [15:0] udp_rec_data_length, // tx part (* MARK_DEBUG="true" *)input wire send_req, @@ -81,7 +81,7 @@ module axis_mac // RX signals reg [10:0] udp_rec_ram_read_addr; wire [7:0] udp_rec_ram_rdata; - wire [15:0] udp_rec_data_length; + wire udp_rec_data_valid; mac_top mac_top0 (