debugging a module and its wrappers

This commit is contained in:
otroubi
2026-07-22 22:06:44 +03:00
parent e06ef3a16b
commit 8648747380
2 changed files with 13 additions and 11 deletions

View File

@ -53,10 +53,10 @@ module wrapper_controller_dma
output logic dac_rst,
output logic adc_rst,
axis_if.slave s_axis_read_data,
axis_if.master m_axis_write_data,
axis_if.master m_axis_read_data,
axis_if.slave s_axis_write_data,
axi4_if.slave s_axi
axi4_if.master m_axi
);
axis_if #(
@ -160,10 +160,10 @@ axi_dma_wrapper_inst
.rst(!rst_n),
.s_axis_read_desc(m_axis_desc_read),
.m_axis_read_desc_status(s_axis_status_read),
.m_axis_read_data(s_axis_read_data),
.m_axis_read_data(m_axis_read_data),
.s_axis_write_desc(m_axis_desc_write),
.m_axis_write_desc_status(s_axis_status_write),
.s_axis_write_data(m_axis_write_data),
.m_axi(s_axi)
.s_axis_write_data(s_axis_write_data),
.m_axi(m_axi)
);
endmodule

View File

@ -106,6 +106,8 @@ module tb_controller_wrapper_axil #(
input wire m_axi_rlast,
input wire m_axi_rvalid,
output wire m_axi_rready
);
logic rst_n;
@ -243,7 +245,7 @@ axi4_if #(
.DATA_W(AXI_DATA_WIDTH),
.ID_W (AXI_ID_WIDTH),
.USER_W(AXI_USER_WIDTH)
) s_axi (
) m_axi (
.aclk(ctrl_clk),
.aresetn(rst_n)
);
@ -258,7 +260,7 @@ axi4_if_to_flat #(
.ID_W (AXI_ID_WIDTH),
.USER_W (AXI_USER_WIDTH)
) u_axi_if_to_flat (
.s_axi(s_axi),
.s_axi(m_axi),
.m_axi_awid (m_axi_awid),
.m_axi_awaddr (m_axi_awaddr),
@ -362,10 +364,10 @@ axi4_if_to_flat #(
.dac_rst(dac_rst),
.adc_rst(adc_rst),
.s_axis_read_data(dma_read_data),
.m_axis_write_data(dma_write_data),
.m_axis_read_data(dma_read_data),
.s_axis_write_data(dma_write_data),
.s_axi(s_axi)
.m_axi(m_axi)
);
endmodule : tb_controller_wrapper_axil